Parallel compiled event driven VHDL simulation

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Parallel compiled event driven VHDL simulation

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International Conference on Supercomputing archive
Proceedings of the 12th international conference on Supercomputing table of contents

Melbourne, Australia

Pages: 297 - 304

Year of Publication: 1998

ISBN:0-89791-998-X

Authors

V. Krishnaswamy	Intel Corporation, JFT 103, 2111, NE 25th Ave, Hillsboro, OR
P. Banerjee	Northwestern University, Center for Parallel and Dist. Computing, 2145 Sheridan Road, Evanston, IL

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 15, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Robert S. French , Monica S. Lam , Jeremy R. Levitt , Kunle Olukotun, A general method for compiling event-driven simulations, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.151-156, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217522]
	3	S. Devadas, K. Keutzer, S. Malik, and A. Wang, "Event Suppression: Improving the Efficiency of Timing Simulation for Synchronous Digital Circuits," IEEE 7kansactions on Computer Aided Design of Integrated Circuits and Systems, vol. 16, pp. 814- 822, June 1994.
	4	G. D. Peterson and J. C. Willis, "A taxonomy of parallel VHDL simulation techniques," in VHDL International User's Forum, 1995.
	5	Venkatram Krishnaswamy , Prithviraj Banerjee, Actor based parallel VHDL simulation using time warp, Proceedings of the tenth workshop on Parallel and distributed simulation, p.135-142, May 22-24, 1996, Philadelphia, Pennsylvania, United States
	6	Kevin L. Kapp , Thomas C. Hartrum , Tom S. Wailes, An improved cost function for static partitioning of parallel circuit simulations using a conservative synchronization protocol, Proceedings of the ninth workshop on Parallel and distributed simulation, p.78-85, June 13-16, 1995, Lake Placid, New York, United States
	7	Venkatram Krishnaswamy , Rajesh Gupta , Prithviraj Banerjee, Implications of VHDL timing models on simulation and software synthesis, Journal of Systems Architecture: the EUROMICRO Journal, v.44 n.1, p.23-36, Oct. 1997 [doi>10.1016/1383-7621(97)80001-X]
	8	Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
	9	E. Smith, B. Underwood, and M. Mercer, "An analysis of several approaches to circuit partitioning for parallel logic simulation," in Proc. of Int'l Conf. on Computer Design, pp. 664-667, IEEE, 1987.
	10	Robert Bernard Mueller-Thuns, Parallel processing for vlsi simulation, 1990
	11	Pran Kurup , Taher Abbasi, Logic synthesis using Synopsys (2nd ed.), Kluwer Academic Publishers, Norwell, MA, 1997
	12	Venkatram Krishnaswamy , Gagan Hasteer , Prithviraj Banerjee, Load Balancing and Workload Minimization Of Overlapping Parallel Tasks, Proceedings of the international Conference on Parallel Processing, p.272-279, August 11-15, 1997
	13	Venkatram Krishnaswamy, Parallel algorithms for VHDL simulation, University of Illinois at Urbana-Champaign, Champaign, IL, 1997