Multipath execution

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Multipath execution: opportunities and limits

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International Conference on Supercomputing archive
Proceedings of the 12th international conference on Supercomputing table of contents

Melbourne, Australia

Pages: 101 - 108

Year of Publication: 1998

ISBN:0-89791-998-X

Authors

Pritpal S. Ahuja	Depts. of Computer Science, Princeton University, Princeton, New Jersey
Kevin Skadron	Depts. of Computer Science, Princeton University, Princeton, New Jersey
Margaret Martonosi	Depts. of Electrical Engineering, Princeton University, Princeton, New Jersey
Douglas W. Clark	Depts. of Computer Science, Princeton University, Princeton, New Jersey

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 21, Citation Count: 9

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. Burger, T. M. Austin, and S. Bennett. Evaluating future microprocessors: the SimpleScalar tool set. Tech. Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept., July 1996.
	2	I-Cheng K. Chen , John T. Coffey , Trevor N. Mudge, Analysis of branch prediction via data compression, Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, p.128-137, October 01-04, 1996, Cambridge, Massachusetts, United States
	3	L. Gwennap. Digital 21264 sets new standard. Microprocessor Report, pages 11-16, Oct. 28, 1996.
	4	T.H. Heil and J. E. Smith. Selective dual path execution. Tech. report, Univ. of Wisconsin-Madison Dept. of Elec. & Comp. Eng., Nov. 1996.
	5	S. Hily , A. Seznec, Branch Prediction and Simultaneous Multithreading, Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques, p.169, October 20-23, 1996
	6	Erik Jacobsen , Eric Rotenberg , J. E. Smith, Assigning confidence to conditional branch predictions, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.142-152, December 02-04, 1996, Paris, France
	7	Stéphan Jourdan , Jared Stark , Tse-Hao Hsing , Yale N. Patt, Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution, International Journal of Parallel Programming, v.25 n.5, p.363-383, Oct. 1997 [doi>10.1007/BF02699883]
	8	Artur Klauser , Abhijit Paithankar , Dirk Grunwald, Selective eager execution on the PolyPath architecture, Proceedings of the 25th annual international symposium on Computer architecture, p.250-259, June 27-July 02, 1998, Barcelona, Spain
	9	James Laudon , Anoop Gupta , Mark Horowitz, Interleaving: a multithreading technique targeting multiprocessors and workstations, Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, p.308-318, October 05-07, 1994, San Jose, California, United States
	10	S. McFarling. Combining branch predictors. Tech. Note TN-36, DEC WRL, June 1993.
	11	Jim Pierce , Trevor Mudge, Wrong-path instruction prefetching, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.165-175, December 02-04, 1996, Paris, France
	12	K. Skadron, P. S. Ahuja, M. Martonosi, and D. W. Clark. Improving prediction for procedure returns with return-address-stack repair mechanisms. Tech. Report TR-577-98, Princeton Dept. of Comp. Sci., Mar. 1998.
	13	K. Skadron, P. S. Ahuja, M. Martonosi, and D. W. Clark. Tradeoffs among branch prediction, instruction-window size, and cache size. Tech. Report TR-578-98, Princeton Dept. of Comp. Sci., April 1998.
	14	Tse-Yu Yeh , Yale N. Patt, A comparison of dynamic branch predictors that use two levels of branch history, Proceedings of the 20th annual international symposium on Computer architecture, p.257-266, May 16-19, 1993, San Diego, California, United States
	15	Dean M. Tullsen , Susan J. Eggers , Joel S. Emer , Henry M. Levy , Jack L. Lo , Rebecca L. Stamm, Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, Proceedings of the 23rd annual international symposium on Computer architecture, p.191-202, May 22-24, 1996, Philadelphia, Pennsylvania, United States
	16	G. Tyson, K. Lick, and M. Farrens. Limited dual path execution. Tech. Report CSE-TR-346-97, University of Michigan, EECS Dept., 1991.
	17	Augustus K. Uht , Vijay Sindagi , Kelley Hall, Disjoint eager execution: an optimal form of speculative execution, Proceedings of the 28th annual international symposium on Microarchitecture, p.313-325, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	18	Steven Wallace , Brad Calder , Dean M. Tullsen, Threaded multiple path execution, Proceedings of the 25th annual international symposium on Computer architecture, p.238-249, June 27-July 02, 1998, Barcelona, Spain

CITED BY 9

	Matthew C. Chidester , Alan D. George , Matthew A. Radlinski, Multiple-path execution for chip multiprocessors, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.1-2, p.33-52, July 2003
	Artur Klauser , Dirk Grunwald, Instruction fetch mechanisms for multipath execution processors, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.38-47, November 16-18, 1999, Haifa, Israel
	Kevin Skadron , Pritpal S. Ahuja , Margaret Martonosi , Douglas W. Clark, Improving prediction for procedure returns with return-address-stack repair mechanisms, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.259-271, November 1998, Dallas, Texas, United States
	Kevin Skadron , Pritpal S. Ahuja , Margaret Martonosi , Douglas W. Clark, Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques, IEEE Transactions on Computers, v.48 n.11, p.1260-1281, November 1999
	Resit Sendag , Ying Chen , David J. Lilja, The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture, IEEE Transactions on Parallel and Distributed Systems, v.16 n.3, p.271-285, March 2005
	Bernard Goossens , David Defour, The instruction register file micro-architecture, Future Generation Computer Systems, v.21 n.5, p.767-773, May 2005
	Ahmed S. Al-Zawawi , Vimal K. Reddy , Eric Rotenberg , Haitham H. Akkary, Transparent control independence (TCI), ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	Shan Lu , Pin Zhou , Wei Liu , Yuanyuan Zhou , Josep Torrellas, PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.38-52, December 09-13, 2006
	Hyesoon Kim , Jose A. Joao , Onur Mutlu , Yale N. Patt, Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.53-64, December 09-13, 2006