A performance study of out-of-order vector architectures and short registers

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

A performance study of out-of-order vector architectures and short registers

Full text

Pdf (1.09 MB)

Source

International Conference on Supercomputing archive
Proceedings of the 12th international conference on Supercomputing table of contents

Melbourne, Australia

Pages: 37 - 44

Year of Publication: 1998

ISBN:0-89791-998-X

Authors

Luis Villa	Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya-Barcelona, Spain and Centro de Investigación en Cómputo, Instituto Politénico Nacional, México D.F.
Roger Espasa	Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya-Barcelona, Spain
Mateo Valero	Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya-Barcelona, Spain

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 17, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/277830.277844 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Akihiro Iwaya and Tadashi Watanabe. The parallel processing feature of the NEC SX-3 supercomputer system. Intl. Journal of High Speed Computing, 3(32z4):187-197, 1991.
	2	Wilfried Oed, Cray Y-MP C90: system features and early benchmark results, Parallel Computing, v.18 n.9, p.947-954, Aug. 1992 [doi>10.1016/0167-8191(92)90039-A]
	3	Luis Villa , Roger Espasa , Mateo Valero, Effective Usage of Vector Registers in Advanced Vector Architectures, Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques, p.250, November 11-15, 1997
	4	R. Espasa , M. Valero , D. Padua , M. Jimenez , E. Ayguade, Quantitative analysis of vector code, Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing, p.452, January 25-27, 1995
	5	Luis Villa , Roger Espasa , Mateo Valero, Effective Usage of Vector Registers in Advanced Vector Architectures, Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques, p.250, November 11-15, 1997
	6	R. Espasa , M. Valero, Decoupled vector architectures, Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, p.281, February 03-07, 1996
	7	Roger Espasa , Mateo Valero, Multithreaded Vector Architectures, Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture, p.237, February 01-05, 1997
	8	Roger Espasa , Mateo Valero , James E. Smith, Out-of-order vector architectures, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.160-170, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	9	Convex Press, Richardson, Texas, U.S.A. CONVEX Architecture Reference Manual (C Series), sixth edition, April 1992.
	10	Kenneth C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, v.16 n.2, p.28-40, April 1996 [doi>10.1109/40.491460]
	11	Alex Peleg , Uri Weiser, MMX Technology Extension to the Intel Architecture, IEEE Micro, v.16 n.4, p.42-50, August 1996 [doi>10.1109/40.526924]
	12	Ruby B. Lee, Subword Parallelism with MAX-2, IEEE Micro, v.16 n.4, p.51-59, August 1996 [doi>10.1109/40.526925]
	13	Marc Tremblay , J. Michael O'Connor , Venkatesh Narayanan , Liang He, VIS Speeds New Media Processing, IEEE Micro, v.16 n.4, p.10-20, August 1996 [doi>10.1109/40.526921]