| Load execution latency reduction |
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International Conference on Supercomputing
archive
Proceedings of the 12th international conference on Supercomputing
table of contents
Melbourne, Australia
Pages: 29 - 36
Year of Publication: 1998
ISBN:0-89791-998-X
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Authors
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Bryan Black
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Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
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Brian Mueller
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Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
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Stephanie Postal
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Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
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Ryan Rakvic
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Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
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Noppanunt Utamaphethai
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Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
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John Paul Shen
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Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
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| Bibliometrics |
Downloads (6 Weeks): 4, Downloads (12 Months): 24, Citation Count: 9
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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David Callahan , Ken Kennedy , Allan Porterfield, Software prefetching, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.40-52, April 08-11, 1991, Santa Clara, California, United States
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William Y. Chen , Scott A. Mahlke , Pohua P. Chang , Wen-mei W. Hwu, Data access microarchitectures for superscalar processors with compiler-assisted data prefetching, Proceedings of the 24th annual international symposium on Microarchitecture, p.69-73, September 1991, Albuquerque, New Mexico, Puerto Rico
[doi> 10.1145/123465.123478]
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Child, J. Advanced DRAM Architectures vie to Succeed SDRAM. In Computer Design, 65-70, May 1997.
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R. Eickemeyer and S. Vassiliadis, A Load-Instruction Unit for Pipelined Processors. In IBM Journal of Research and Development, Vol. 37, No. 4, 547-564, July 1993.
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IBM Microelectronics Division. PowerPC 604 RISC Micropr9cessor User's Manual, 1994.
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Quinn Jacobson , Eric Rotenberg , James E. Smith, Path-based next trace prediction, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.14-23, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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Lee, J., and Smith, A. Branch Prediction Strategies and Branch Target Buffer Design. In IEEE Computer, 6-22, January 1984.
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Mikko H. Lipasti , Christopher B. Wilkerson , John Paul Shen, Value locality and load value prediction, Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, p.138-147, October 01-04, 1996, Cambridge, Massachusetts, United States
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Margolin, B. Embedded Systems to Benefit from Advances in DRAM Technology. In Computer Design, 76-86, March 1997.
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McFarling, S. Combining Branch Predictors. Technical Report TN-36, Digital Western Research Laboratory, June 1993.
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Andreas Moshovos , Scott E. Breach , T. N. Vijaykumar , Gurindar S. Sohi, Dynamic speculation and synchronization of data dependences, Proceedings of the 24th annual international symposium on Computer architecture, p.181-193, June 01-04, 1997, Denver, Colorado, United States
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Todd C. Mowry , Monica S. Lam , Anoop Gupta, Design and evaluation of a compiler algorithm for prefetching, Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, p.62-73, October 12-15, 1992, Boston, Massachusetts, United States
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