MetaCore: an application specific DSP development system

ABSTRACT

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.

REFERENCES

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• 2: G. Intrater, D. Biran, "Application Specific Microprocessors'', Proc. IEEE Int'l Conference on Computer Design: VLSI in Computers ~ Processors, 1990.
• 3: R. Woudsma, R. A. M. Beltman, et al.,"EPICS, a Flexible Approach to Embedded DSP Cores", Proc.{nt'l Conference on Signal Processing Applications ~4 Technology (ICSPAD, Oct. 1994, pp. 506-511.
• 4: Jun Sato, et al., "PEAS-I: A Hardware/Software Codesign System for ASIP Development", IEICE Trans. Fundamentals, Mar. 1994, pp. 483-491.
• 5: Mario R. Barbacci, "Instruction Set Processor Specifications(ISPS): The Notation and Its Applications", IEEE Trans. CAD, Jan. 1981, pp. 24-40.
• 6: Gerry Kane, MIPS RISC architecture, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

General Terms:
Design, Experimentation, Measurement, Performance, Theory

Keywords:
high-level synthesis, telecommunication