Full-chip verification methods for DSM power distribution systems

ABSTRACT

Power distribution verification is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased load and reduced tolerances of DSM circuits, more failures are being seen due to poorly designed power distribution systems. This paper describes an efficient approach for the verification of power distribution at the full-chip transistor level based on a combination of hierarchical static and dynamic techniques. Application of the methodology on practical design examples will be provided. We will also demonstrate the necessity of an analysis at the full-chip transistor level to verify the complex interactions between different design blocks based on static and dynamic effects.

REFERENCES

• 1: Lightning Vl.2 Power Distribution Verification Manual. Simplex Solutions, Inc., 1997.
• 2: Chi-Ying Tsui , Radu Marculescu , Diana Marculescu , Massoud Pedram, Improving the efficiency of power simulators by input vector compaction, Proceedings of the 33rd annual conference on Design automation, p.165-168, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240549]
• 3: Joseph N. Kozhaya , Farid N. Najm, Accurate power estimation for large sequential circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.488-493, November 09-13, 1997, San Jose, California, United States
• 4: Yong Je Lim , Kyung-Im Son , Heung-Joon Park , Mani Soma, A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits, Proceedings of the 33rd annual conference on Design automation, p.445-450, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240603]
• 5: Li-Pen Yuan , Chin-Chi Teng , Sung-Mo Kang, Statistical estimation of average power dissipation in sequential circuits, Proceedings of the 34th annual conference on Design automation, p.377-382, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266175]
• 6: H.J.M. Veendrick. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer August 1984~
• 7: Radu Marculescu , Diana Marculescu , Massoud Pedram, Hierarchical sequence compaction for power estimation, Proceedings of the 34th annual conference on Design automation, p.570-575, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266287]
• 8: Angela Krstić , Kwang-Ting Cheng, Vector generation for maximum instantaneous current through supply lines for CMOS circuits, Proceedings of the 34th annual conference on Design automation, p.383-388, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266176]
• 9: Subodh Gupta , Farid N. Najm, Power macromodeling for high level power estimation, Proceedings of the 34th annual conference on Design automation, p.365-370, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266171]
• 10: Alessandro Bogliolo , Luca Benini , Giovanni De Micheli , Bruno Riccó, Gate-level power and current simulation of CMOS integrated circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.473-488, Dec. 1997 [doi>10.1109/92.645074]
• 11: Thunder Vl.2 Transistor-Level Verification Manual. Simplex Solution ,Inc.,1997.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability

Additional Classification:
  C. Computer Systems Organization

  J. Computer Applications

General Terms:
Design, Performance, Theory, Verification

Keywords:
IR-drop, PowerPC, power distribution network, reliability