| Design and analysis of power distribution networks in PowerPC microprocessors |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 35th annual Design Automation Conference
table of contents
San Francisco, California, United States
Pages: 738 - 743
Year of Publication: 1998
ISBN:0-89791-964-5
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Authors
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Abhijit Dharchoudhury
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Advanced Tools Group, Advanced System Technologies Lab, Motorola, Austin, TX
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Rajendran Panda
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Advanced Tools Group, Advanced System Technologies Lab, Motorola, Austin, TX
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David Blaauw
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Advanced Tools Group, Advanced System Technologies Lab, Motorola, Austin, TX
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Ravi Vaidyanathan
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Advanced Tools Group, Advanced System Technologies Lab, Motorola, Austin, TX
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Bogdan Tutuianu
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Somerset Design Center, Austin, TX
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David Bearden
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Somerset Design Center, Austin, TX
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Downloads (6 Weeks): 15, Downloads (12 Months): 64, Citation Count: 53
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ABSTRACT
We present a methodology for the design and analysis of power grids in the PowerPC™ microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology to the PowerPC™ 750 microprocessor is presented.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 53
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Rajendran Panda , David Blaauw , Rajat Chaudhry , Vladimir Zolotov , Brian Young , Ravi Ramaraju, Model and analysis for combined package and on-chip power grid simulation, Proceedings of the 2000 international symposium on Low power electronics and design, p.179-184, July 25-27, 2000, Rapallo, Italy
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Joon-Seo Yim , Seong-Ok Bae , Chong-Min Kyung, A floorplan-based planning methodology for power and clock distribution in ASICs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.766-771, June 21-25, 1999, New Orleans, Louisiana, United States
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Haihua Su , Frank Liu , Anirudh Devgan , Emrah Acar , Sani Nassif, Full chip leakage estimation considering power supply and temperature variations, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
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Hongyu Chen , Chung-Kuan Cheng , Andrew B. Kahng , Makoto Mori , Qinke Wang, Optimal planning for mesh-based power distribution, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.444-449, January 27-30, 2004, Yokohama, Japan
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Min Zhao , Kaushik Gala , Vladimir Zolotov , Yuhong Fu , Rajendran Panda , R. Ramkumar , Bhuwan Agrawal, Worst case clock skew under power supply variations, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
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Masato Iwabuchi , Noboru Sakamoto , Yasushi Sekine , Takashi Omachi, A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design, Proceedings of the 1999 international symposium on Physical design, p.9-15, April 12-14, 1999, Monterey, California, United States
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Min Zhao , Rajendran V. Panda , Sachin S. Sapatnekar , Tim Edwards , Rajat Chaudhry , David Blaauw, Hierarchical analysis of power distribution networks, Proceedings of the 37th conference on Design automation, p.150-155, June 05-09, 2000, Los Angeles, California, United States
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Sanjay Pant , David Blaauw , Vladimir Zolotov , Savithri Sundareswaran , Rajendran Panda, A stochastic approach To power grid analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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Jingjing Fu , Zuying Luo , Xianlong Hong , Yici Cai , Sheldon X.-D. Tan , Zhu Pan, A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.505-510, January 27-30, 2004, Yokohama, Japan
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Min Zhao , Yuhong Fu , Vladimir Zolotov , Savithri Sundareswaran , Rajendran Panda, Optimal placement of power supply pads and pins, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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D. T. Blaauw , A. Dharchoudhury , R. Panda , S. Sirichotiyakul , C. Oh , T. Edwards, Emerging power management tools for processor design, Proceedings of the 1998 international symposium on Low power electronics and design, p.143-148, August 10-12, 1998, Monterey, California, United States
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Min Zhao , Rajendran Panda , Savithri Sundareswaran , Shu Yan , Yuhong Fu, A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Praveen Ghanta , Sarma Vrudhula , Sarvesh Bhardwaj , Rajendran Panda, Stochastic variational analysis of large power grids considering intra-die correlations, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Min Zhao , Rajendran Panda , Ben Reschke , Yuhong Fu , Trudi Mewett , Sri Chandrasekaran , Savithri Sundareswaran , Shu Yan, On-chip decoupling capacitance and P/G wire co-optimization for dynamic noise, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
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Hongyu Chen , Chung-Kuan Cheng , Andrew B. Kahng , Ion Mandoiu , Qinke Wang , Bo Yao, The Y-Architecture for On-Chip Interconnect: Analysis and Methodology, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.13, November 09-13, 2003
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