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Reducing power in high-performance microprocessors
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents
San Francisco, California, United States
Pages: 732 - 737  
Year of Publication: 1998
ISBN:0-89791-964-5
Authors
Vivek Tiwari  Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
Deo Singh  Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
Suresh Rajgopal  Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
Gaurav Mehta  Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
Rakesh Patel  Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
Franklin Baez  Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 21,   Downloads (12 Months): 142,   Citation Count: 64
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ABSTRACT

Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
ACPI home page. http://www, teleport, com/~acpi.
 
2
$. Borkar, Intel Corp. Personal communication.
 
3
A. Chandrakasan, R. Brodersen. Minimizing power consumption in digital CMOS circuits?roceedings of the IEEE83(4), April 1995.
 
4
S. Ellis. Power management in notebook computer't'roc. Silicon Valley Personal Computing Design Conference, July 1991.
 
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L. Gwennap. Power issues may limit future CPUs. Microprocessor Report, 10( 1 0), August 1996.
 
6
Intel Power Monitor home page. http://developer, intel, com/ial./ipm.
 
7
J. Schutz. A 3.3V 0.6um BiCMOS SuperScalar Microprocessor. I$$CC Digest of Tech. Papers, Feb 1994.
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CITED BY  64

Collaborative Colleagues:
Vivek Tiwari: colleagues
Deo Singh: colleagues
Suresh Rajgopal: colleagues
Gaurav Mehta: colleagues
Rakesh Patel: colleagues
Franklin Baez: colleagues