| Reducing power in high-performance microprocessors |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 35th annual Design Automation Conference
table of contents
San Francisco, California, United States
Pages: 732 - 737
Year of Publication: 1998
ISBN:0-89791-964-5
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Authors
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Vivek Tiwari
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Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
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Deo Singh
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Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
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Suresh Rajgopal
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Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
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Gaurav Mehta
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Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
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Rakesh Patel
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Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
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Franklin Baez
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Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA
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Downloads (6 Weeks): 21, Downloads (12 Months): 142, Citation Count: 64
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ABSTRACT
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 64
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Hongbo Yang , Guang R. Gao , Clement Leung, On achieving balanced power consumption in software pipelined loops, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
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Radu Marculescu , Diana Marculescu , Massoud Pedram, Non-stationary effects in trace-driven power analysis, Proceedings of the 1999 international symposium on Low power electronics and design, p.133-138, August 16-17, 1999, San Diego, California, United States
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A. Hemani , T. Meincke , S. Kumar , A. Postula , T. Olsson , P. Nilsson , J. Oberg , P. Ellervee , D. Lundqvist, Lowering power consumption in clock by using globally asynchronous locally synchronous design style, Proceedings of the 36th ACM/IEEE conference on Design automation, p.873-878, June 21-25, 1999, New Orleans, Louisiana, United States
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Alper Buyuktosunoglu , David H. Albonesi , Stanley Schuster , David Brooks , Pradip Bose , Peter Cook, Power-efficient issue queue design, Power aware computing, Kluwer Academic Publishers, Norwell, MA, 2002
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Luca Benini , Alessandro Bogliolo , Giovanni De Micheli, Dynamic power management of electronic systems, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.696-702, November 08-12, 1998, San Jose, California, United States
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Masato Iwabuchi , Noboru Sakamoto , Yasushi Sekine , Takashi Omachi, A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design, Proceedings of the 1999 international symposium on Physical design, p.9-15, April 12-14, 1999, Monterey, California, United States
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David M. Brooks , Pradip Bose , Stanley E. Schuster , Hans Jacobson , Prabhakar N. Kudva , Alper Buyuktosunoglu , John-David Wellman , Victor Zyuban , Manish Gupta , Peter W. Cook, Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors, IEEE Micro, v.20 n.6, p.26-44, November 2000
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Yingmin Li , Mark Hempstead , Patrick Mauro , David Brooks , Zhigang Hu , Kevin Skadron, Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
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Yongseok Cheon , Pei-Hsin Ho , Andrew B. Kahng , Sherief Reda , Qinke Wang, Power-aware placement, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Mondira Deb Pant , Pankaj Pant , D. Scott Wills , Vivek Tiwari, An architectural solution for the inductive noise problem due to clock-gating, Proceedings of the 1999 international symposium on Low power electronics and design, p.255-257, August 16-17, 1999, San Diego, California, United States
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Hao Yu , Yiyu Shi , Lei He , Tanay Karnik, Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
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