Power considerations in the design of the Alpha 21264 microprocessor

ABSTRACT

Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized to help manage power dissipation. In addition, the electrical design of the power, ground, and clock networks is presented.

REFERENCES

• 1: Dobberpuhl, D., et al., "A 200 MHz 64b Dual-Issue CMOS Microprocessor," IEEE Journal of Solid State Circuits, vol. 27, no. 11, Nov., 1992.
• 2: Benschneider, B., et al., "A 300-MHz 64b Quad-Issue CMOS RISC Microprocessor," IEEE Journal of Solid State Circuits, vol. 30, no. 11, Nov., 1995.
• 3: Gieseke, B., et al., "A 600 MHz Superscaler RISC Microprocessor With Out-of-Order Execution," ISSCC Digest of Technical Papers, pp. 222-223, Feb., 1996.
• 4: William J. Grundmann , Dan Dobberpuhl , Randy L. Allmon , Nicholas L. Rethman, Designing high performance CMOS microprocessors using full custom techniques, Proceedings of the 34th annual conference on Design automation, p.722-727, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266353]
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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION

Additional Classification:
  C. Computer Systems Organization

  J. Computer Applications

General Terms:
Design, Measurement, Performance, Theory

Keywords:
PLA-style logic blocks, programmable logic devices, technology mapping