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A power macromodeling technique based on power sensitivity
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents
San Francisco, California, United States
Pages: 678 - 683  
Year of Publication: 1998
ISBN:0-89791-964-5
Authors
Zhanping Chen  School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Kaushik Roy  School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 18,   Citation Count: 14
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ABSTRACT

In this paper, we propose a novel power macromodeling technique for high level power estimation based on power sensitivity. Power sensitivity defines the change in average power due to changes in the input signal specification. The contribution of this work is that we can use only a few points to construct a complicated power surface in the specification-space. With such a power surface, we can easily obtain the power dissipation under any distribution of primary inputs. The advantages of our technique are two-fold. First, the required parameters corresponding to each representative point can be efficiently obtained by only one symbolic power estimation run or by only one Monte Carlo based statistical power estimation process. This stems from the fact that power sensitivity can be obtained as a by-product of probabilistic or statistical power estimation runs. Second, the memory requirements for the macromodel are reduced to O(dn), where n is the number of primary inputs of a circuit and d is the number of representative points (d can be as small as 1 in some cases). Results on a number of benchmark circuits demonstrate the effectiveness of our technique.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A.P. Chandrakasan, S.Sheng, and R.W.Brodersen,"Low- Power CMOS Digital Design," Journal of Solid-State Circuits, Vok27, No.4, pp.473-483, April,1992.
 
2
Z. Chen, IC Roy, and T.-L Chou, "Sensitivity of Power Dissipation to Uncertainties in Primary Input Specificatiom Custom Integrated Circuits Conference, pp. 487-490, 1997.
 
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Michael D. Greenberg, 'Advanced Engineering Mathematics,'' New Jersey: Prentice-Hall, 1988.
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M. Nemani and F. Najm, 'Towards a High-Level Power Estimation Capability," IEEE Trans. on CAD, pp. 58~598, June 1996.
 
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S.R. PoweH and P. M. Chau, '~stimating Power Dissipation of VLSI Signal Processing Chips: The PFA Technique,"VLSl Signal Processing IV, pp. 250-259, 1990.
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K. ROy and S. Pmsad, "Circuit Activity Based Logic Synthesis for Low Power Reliable Operations," IEEE Trans. on VLSI Systems, pp. 503-513, De~ 1993.

CITED BY  14

Collaborative Colleagues:
Zhanping Chen: colleagues
Kaushik Roy: colleagues