| A power macromodeling technique based on power sensitivity |
| Full text |
Pdf
(473 KB)
|
| Source
|
Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 35th annual Design Automation Conference
table of contents
San Francisco, California, United States
Pages: 678 - 683
Year of Publication: 1998
ISBN:0-89791-964-5
|
|
Authors
|
|
Zhanping Chen
|
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
|
|
Kaushik Roy
|
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 4, Downloads (12 Months): 18, Citation Count: 14
|
|
|
ABSTRACT
In this paper, we propose a novel power macromodeling technique for high level power estimation based on power sensitivity. Power sensitivity defines the change in average power due to changes in the input signal specification. The contribution of this work is that we can use only a few points to construct a complicated power surface in the specification-space. With such a power surface, we can easily obtain the power dissipation under any distribution of primary inputs. The advantages of our technique are two-fold. First, the required parameters corresponding to each representative point can be efficiently obtained by only one symbolic power estimation run or by only one Monte Carlo based statistical power estimation process. This stems from the fact that power sensitivity can be obtained as a by-product of probabilistic or statistical power estimation runs. Second, the memory requirements for the macromodel are reduced to O(dn), where n is the number of primary inputs of a circuit and d is the number of representative points (d can be as small as 1 in some cases). Results on a number of benchmark circuits demonstrate the effectiveness of our technique.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
A.P. Chandrakasan, S.Sheng, and R.W.Brodersen,"Low- Power CMOS Digital Design," Journal of Solid-State Circuits, Vok27, No.4, pp.473-483, April,1992.
|
| |
2
|
Z. Chen, IC Roy, and T.-L Chou, "Sensitivity of Power Dissipation to Uncertainties in Primary Input Specificatiom Custom Integrated Circuits Conference, pp. 487-490, 1997.
|
| |
3
|
Zhanping Chen , Kaushik Roy , Tan-Li Chou, Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.40-44, November 09-13, 1997, San Jose, California, United States
|
| |
4
|
Tan-Li Chou , Kaushik Roy , Sharat Prasad, Estimation of circuit activity considering signal correlations and simultaneous switching, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.300-303, November 06-10, 1994, San Jose, California, United States
|
| |
5
|
Michael D. Greenberg, 'Advanced Engineering Mathematics,'' New Jersey: Prentice-Hall, 1988.
|
 |
6
|
|
| |
7
|
|
 |
8
|
Diana Marculescu , Radu Marculescu , Massoud Pedram, Information theoretic measures of energy consumption at register transfer level, Proceedings of the 1995 international symposium on Low power design, p.81-86, April 23-26, 1995, Dana Point, California, United States
[doi> 10.1145/224081.224096]
|
 |
9
|
Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin, Energy characterization based on clustering, Proceedings of the 33rd annual conference on Design automation, p.702-707, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240651]
|
| |
10
|
M. Nemani and F. Najm, 'Towards a High-Level Power Estimation Capability," IEEE Trans. on CAD, pp. 58~598, June 1996.
|
| |
11
|
S.R. PoweH and P. M. Chau, '~stimating Power Dissipation of VLSI Signal Processing Chips: The PFA Technique,"VLSl Signal Processing IV, pp. 250-259, 1990.
|
 |
12
|
Qinru Qiu , Qing Wu , Massoud Pedram , Chih-Shun Ding, Cycle-accurate macro-models for RT-level power analysis, Proceedings of the 1997 international symposium on Low power electronics and design, p.125-130, August 18-20, 1997, Monterey, California, United States
[doi> 10.1145/263272.263305]
|
| |
13
|
Anand Raghunathan , Sujit Dey , Niraj K. Jha, Register-transfer level estimation techniques for switching activity and power consumption, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.158-165, November 10-14, 1996, San Jose, California, United States
|
| |
14
|
K. ROy and S. Pmsad, "Circuit Activity Based Logic Synthesis for Low Power Reliable Operations," IEEE Trans. on VLSI Systems, pp. 503-513, De~ 1993.
|
CITED BY 14
|
|
|
|
|
Zhanping Chen , Kaushik Roy , Edwin K. P. Chong, Estimation of power sensitivity in sequential circuits with power macromodeling application, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.468-472, November 08-12, 1998, San Jose, California, United States
|
|
|
Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, Proceedings of the 1998 international symposium on Low power electronics and design, p.239-244, August 10-12, 1998, Monterey, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Alex K. Jones , Raymond Hoare , Dara Kusic , Gayatri Mehta , Josh Fazekas , John Foster, Reducing power while increasing performance with supercisc, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.3, p.658-686, August 2006
|
|
|
|
|
|
Swapna Dontharaju , Shenchih Tung , James T. Cain , Leonid Mats , Marlin H. Mickle , Alex K. Jones, A design automation and power estimation flow for RFID systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.14 n.1, p.1-31, January 2009
|
|
|
|
|
|
|
|