Functional verification of large ASICs

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Functional verification of large ASICs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents

San Francisco, California, United States

Pages: 650 - 655

Year of Publication: 1998

ISBN:0-89791-964-5

Authors

Adrian Evans	Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada
Allan Silburt	Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada
Gary Vrckovnik	Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada
Thane Brown	Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada
Mario Dufresne	Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada
Geoffrey Hall	Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada
Tung Ho	Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada
Ying Liu	Nortel, P.O. Box 3511, Station C, Ottawa, Ontario, K1Y-4H7, Canada

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 28, Citation Count: 16

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASICs designed at Nortel. These devices marked a transition point in methodology as verification took front and centre on the critical path of the ASIC schedule. Both the simulation and emulation strategies are presented. The simulation methodology introduced new techniques such as ASIC sub-system level behavioural modeling, large multi-chip simulations, and random pattern simulations. The emulation strategy was based on a plan that consisted of integrating parts of the real software on the emulated system. This paper describes how these technologies were deployed, analyzes the bugs that were found and highlights the bottlenecks in functional verification as systems become more complex.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Allan Silburt , Ian Perryman , Janick Bergeron , Stacy Nichols , Mario Dufresne , Greg Ward, Accelerating concurrent hardware design with behavioural modelling and system simulation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.528-533, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217582]
	2	Miklosz, John, "Meeting the Crisis in Confidence That Complexity Causes", Integrated Systems Design, August 1997.
	3	Adrian Evans , Allan Silburt , Gary Vrckovnik , Thane Brown , Mario Dufresne , Geoffrey Hall , Tung Ho , Ying Liu, Functional verification of large ASICs, Proceedings of the 35th annual conference on Design automation, p.650-655, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277210]

CITED BY 16

	Murali Kudlugi , Soha Hassoun , Charles Selvidge , Duaine Pryor, A transaction-based unified simulation/emulation architecture for functional verification, Proceedings of the 38th conference on Design automation, p.623-628, June 2001, Las Vegas, Nevada, United States
	Tony Givargis , Frank Vahid , Jörg Henkel, A hybrid approach for core-based system-level power modeling, Proceedings of the 2000 conference on Asia South Pacific design automation, p.141-146, January 2000, Yokohama, Japan
	Adrian Evans , Allan Silburt , Gary Vrckovnik , Thane Brown , Mario Dufresne , Geoffrey Hall , Tung Ho , Ying Liu, Functional verification of large ASICs, Proceedings of the 35th annual conference on Design automation, p.650-655, June 15-19, 1998, San Francisco, California, United States
	Frank Vahid , Tony Givargis, The case for a configure-and-execute paradigm, Proceedings of the seventh international workshop on Hardware/software codesign, p.59-63, March 1999, Rome, Italy
	Tun Li , Yang Guo , Si-Kun Li, Automatic circuit extractor for HDL description using program slicing, Journal of Computer Science and Technology, v.19 n.5, p.718-728, September 2004
	Chien-Nan Jimmy Liu , Jing-Yang Jou, An Automatic Controller Extractor for HDL Descriptions at the RTL, IEEE Design & Test, v.17 n.3, p.72-77, July 2000
	Lionel Bening, A two-state methodology for RTL logic simulation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.672-677, June 21-25, 1999, New Orleans, Louisiana, United States
	Yuanbin Guo , Joseph R. Cavallaro, A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems, Journal of VLSI Signal Processing Systems, v.44 n.3, p.195-217, September 2006
	Ghazanfar Asadi , Seyed Ghassem Miremadi , Alireza Ejlali, Fast co-verification of HDL models, Microelectronic Engineering, v.84 n.2, p.218-228, February, 2007
	Shireesh Verma , Ian G. Harris , Kiran Ramineni, Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Yuanbin Guo , Dennis McCain , Joseph R. Cavallaro , Andres Takach, Rapid industrial prototyping and SoC design of 3G/4G wireless systems using an HLS methodology, EURASIP Journal on Embedded Systems, v.2006 n.1, p.18-18, January 2006
	Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph R. Cavallaro, An efficient circulant MIMO equalizer for CDMA downlink: algorithm and VLSI architecture, EURASIP Journal on Applied Signal Processing, v.2006 n.1, p.144-144, 01 January
	Byeong Min , Gwan Choi, Verification Simulation Acceleration UsingCode-Perturbation, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.83-90, Feb/April 2000
	Jun Yuan , Kurt Shultz , Carl Pixley , Hillel Miller , Adnan Aziz, Automatic Vector Generation Using Constraints and Biasing, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.107-120, Feb/April 2000
	Chien-Nan Jimmy Liu , I-Ling Chen , Jing-Yang Jou, An efficient design-for-verification technique for HDLs, Proceedings of the 2001 conference on Asia South Pacific design automation, p.103-108, January 2001, Yokohama, Japan
	Malay K. Ganai , Adnan Aziz, Improved SAT-based Bounded Reachability Analysis, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.729, January 07-11, 2002