TETA: transistor-level engine for timing analysis

ABSTRACT

TETA is an interconnect-centric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and large coupled RC(L) interconnect models. TETA applies a novel compaction for the transistor clusters and employs successive chord iterations to solve the resulting nonlinear equations. These algorithms permit the use of simple SIMO (single input multi-output) N-port interconnect models since macromodel passivity is not required. The successive chord analysis also enables TETA to avoid the N-port matrix factorization during nonlinear iterations and allows the use of simple table look-up models for MOS devices. Complex gates and nonlinear capacitors can be handled without loss of generality.

REFERENCES

• 1: C.L. Ratzlaff, L.T. Pillage, "RICE: Rapid interconnect circuit evaluation using AWE," IEEETCAD, pp. 763-776, 1994.
• 2: K.J. Kerns, "Accurate and stable reduction of RLC networks using split congruence transformations," Ph.D. thesis, U. of Washington, September 1996.
• 3: Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, PRIMA: passive reduced-order interconnect macromodeling algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.58-65, November 09-13, 1997, San Jose, California, United States
• 4: A. Devgan, R.A. Rohrer, "Adaptively controlled explicit integration," IEEE Trans. on CAD, pp. 746-762, June 1994.
• 5: William J. McCalla, Fundamentals of computer-aided circuit simulation, Kluwer, B.V., Deventer, The Netherlands, 1987
• 6: F. Dartu, "Gate and transistor level waveform calculation for timing analysis," Ph.D. thesis, Carnegie Mellon Univ., 1997.
• 7: L.W. Nagel, "SPICE2, a computer program to simulate semiconductor circuits," Tech. Rep. Memo UCB/ERLM520. Univ. of California, Berkeley, May 1975.
• 8: S.Y. Kim, N. Gopal, L.T. Pillage, "Time-domain macromodels for VLSI interconnect analysis," IEEE Trans. on CAD, pp. 1257-1270, October 1994.
• 9: Resve A. Saleh , A. Richard Newton, Mixed-Mode Simulation, Kluwer Academic Publishers, Norwell, MA, 1990
• 10: L.T. Pillage, R.A, Rohrer, C. Visweswariah, "Electronic circuit and system simulation methods," McGraw Hill, 1995.
• 11: A. Devgan, "Dynamic timing simulation," DAC '96 tutorial.
• 12: J.J. Rotman, "An introduction to algebraic topology," Springer-Verlag, 1988.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies
  B.8 Performance and Reliability

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

  G. Mathematics of Computing
  G.4 MATHEMATICAL SOFTWARE
      Subjects: Algorithm design and analysis

  J. Computer Applications

General Terms:
Algorithms, Design, Measurement, Performance, Theory