A BIST scheme for RTL controller-data paths based on symbolic testability analysis

ABSTRACT

This paper introduces a novel scheme for testing register-transfer level controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) which consists of operations mapped to modules in the circuit and variables mapped to registers. This TCDF is used to derive a set of symbolic justification and propagation paths (known as test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDFs, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can be analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Every module in the module library is made random-pattern testable, whenever possible, using gate-level testability insertion techniques. Finally, a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed on the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme in a small number of test cycles at an average area (delay) overhead of only 6.4% (2.5%).

REFERENCES

• 1: M. Abadir and M. Breuer, "Constructing optimal test schedules for VLSI circuits having built-in test hardware," in Proc. Int. Syrup. Fault Tolerant Computing, pp. 165-170, June 1985.
• 2: M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, IE Press, New York, 1990.
• 3: H. Schnurmann, E. Lindblom, and R.G. Carpenter, "The weighted random test-pattern generator," IEEE Truns. Comput., vol. C-24, pp. 695-700, July 1975.
• 4: Chih-Jen Lin , Yervant Zorian , Sudipta Bhawmik, PSBIST: A Partial-Scan Based Built-In Self-Test Scheme, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.507-516, October 17-21, 1993
• 5: Scott S. K. Chiu , Christos A. Papachristou, A Built-In Self-Testing Approach for Minimizing Hardware Overhead, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.282-285, October 14-16, 1991
• 6: Christos A. Papachristou , Joan Carletta, Test Synthesis in the Behavioral Domain, Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test, p.693-702, October 21-25, 1995
• 7: M. Nourani , J. Carletta , C. Papachristou, A scheme for integrated controller-datapath fault testing, Proceedings of the 34th annual conference on Design automation, p.546-551, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266280]
• 8: N. Mukherjee , H. Kassab , J. Rajski , J. Tyszer, Arithmetic built-in self test for high-level synthesis, Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), p.132, April 30-May 03, 1995
• 9: Indradeep Ghosh , Anand Raghunathan , Niraj K. Jha, A design for testability technique for RTL circuits using control/data flow extraction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.329-336, November 10-14, 1996, San Jose, California, United States
• 10: Sandeep Bhatia , Niraj K. Jha, Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.91-96, October 10-12, 1994
• 11: I. Ghosh, A. Raghunathan, and N.K. Jha, "Design for hierarchical testability of RTL circuits obtained by behavioral synthesis," IEEE Truns. Computer-aided Design, vol. 16, pp. 1000-1001, Sept. 1997.
• 12: I. Ghosh, N.K. Jha, and S. Bhawmik, "A BIST scheme for RTL controller-data paths based on symbolic testability analysis," Tech. Rep. CE-J98-005, EE Dept., Princeton Univ.
• 13: LaNae J. Avra, Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.463-472, October 26-30, 1991
• 14: Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
• 15: Prabhakar Goel , Barry C. Rosales, PODEM-X: An automatic test generation system for VLSI logic structures, Proceedings of the 18th conference on Design automation, p.260-268, June 29-July 01, 1981, Nashville, Tennessee, United States
• 16: I. Pomeranz, L.N. Reddy, and S.M. Reddy, "COMPACTEST: A method to generate compact test set for combinational circuits," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1040-1049, July 1993.
• 17: LaNae J. Avra , Edward J. McCluskey, Synthesizing for Scan Dependence in Built-In Self-Testable Designs, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.734-743, October 17-21, 1993
• 18: Preeti R. Panda , Nikil D. Dutt, 1995 high level synthesis design repository, Proceedings of the 8th international symposium on System synthesis, p.170-174, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224537]
• 19: Thomas M. Niermann , Wu-Tung Cheng , Janak H. Patel, Proofs: a fast, memory efficient sequential circuit fault simulator, Proceedings of the 27th ACM/IEEE conference on Design automation, p.535-540, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123396]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Control design

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.2 Input/Output Devices
          Subjects: Channels and controllers
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design
  B.8 Performance and Reliability

  C. Computer Systems Organization

  J. Computer Applications

General Terms:
Design, Experimentation, Measurement, Performance, Theory