MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

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MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents

San Francisco, California, United States

Pages: 495 - 500

Year of Publication: 1998

ISBN:0-89791-964-5

Authors

James Kao	Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
Siva Narendra	Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
Anantha Chandrakasan	Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 68, Citation Count: 46

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to provide adequate performance is difficult because the overall delay characteristics are strongly dependent on the discharge patterns of internal gates. This paper proposes a methodology for sizing the sleep transistor for a large module based on mutual exclusive discharge patterns of internal blocks. This algorithm can be applied at all levels of a circuit hierarchy, where the internal blocks can represent transistors, cells within an array, or entire modules. This methodology will give an upper bound for the sleep transistor size required to meet any performance constraint.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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