Design and optimization of low voltage high performance dual threshold CMOS circuits

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Design and optimization of low voltage high performance dual threshold CMOS circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents

San Francisco, California, United States

Pages: 489 - 494

Year of Publication: 1998

ISBN:0-89791-964-5

Authors

Liqiong Wei	School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN
Zhanping Chen	School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN
Mark Johnson	School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN
Kaushik Roy	School of Electrical and Computer Engineering, Purdue University, W. Lafayette, IN
Vivek De	Microcomputer Research Labs., Intel Corp., Hillsboro, OR

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 53, Citation Count: 43

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ABSTRACT

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.

REFERENCES

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	1	J. D. Meindl, "Low power Microelectronics: Retrospect and Prospect", Proceedings of the IEEE, Vol.83, No.4, pp.619, 1995.
	2	A.P. Chandrakasan, et al.,"Low-Power CMOS Digital Design", IEEE Journal of Solid-State Circuits, Vol.27, No.4, pp.473, 1992.
	3	Pankaj Pant , Vivek De , Abhijit Chatterjee, Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks, Proceedings of the 34th annual conference on Design automation, p.403-408, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266181]
	4	C. Hu, "Device and technology impact on low power electronics", in Low Power Design Methodologies, J.M.Rabaey and M.Pedram, Eds. Norwell, MA:Kluwer,pp21-36, 1996.
	5	B. Davari, et al., "CMOS Scaling for High Performance and Low Power-The Next Ten Years", Proceedings of the IEEE, Vol.83, No.4, pp595, 1995.
	6	Z. Chen, et al., "0.18urn Dual Vt MOSFET Process and Energy-Delay Measurement", IEDM Digest, pp851, 1996.
	7	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	8	S. Mutoh, et al., "I-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS", IEEE Journal of Solid-State Circuits, Vol.30, No.8, pp. 847-853, 1993.
	9	H. Oyamatsu, et al., "Design Methodology of Deep Submicron CMOS Devices for 1V Operation", IEICE Trans. Electron., VOL.E79-C, No.12, pp1720-1724, 1996
	10	A.bdellatif Bellaouar , Mohamed I. Elmasry , Jonathan Allen, Low-Power Digital VLSI Design Circuits and Systems, Kluwer Academic Publishers, Norwell, MA, 1995
	11	M.C. Johnson, K. Roy, and D. Somasekhar 'A model for leakage control by transistor stacking", Technical Report TR-ECE 97-12, Purdue University, Dept. of ECE.
	12	J. Sheu, et. al., "BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors", IEEE J. Solid-State Circuits, SC-22, 1987.
	13	Mark C. Johnson , Kaushik Roy, Datapath scheduling with multiple supply voltages and level converters, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.3, p.227-248, July 1997 [doi>10.1145/264995.264997]

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	Muhammad M. Khellah , M. I. Elmasry, Power minimization of high-performance submicron CMOS circuits using a dual-Vdd dual-Vth (DVDV) approach, Proceedings of the 1999 international symposium on Low power electronics and design, p.106-108, August 16-17, 1999, San Diego, California, United States
	Vijay Sundararajan , Keshab K. Parhi, Low power synthesis of dual threshold voltage CMOS VLSI circuits, Proceedings of the 1999 international symposium on Low power electronics and design, p.139-144, August 16-17, 1999, San Diego, California, United States
	Seongmoo Heo , Kenneth Barr , Mark Hampton , Krste Asanović, Dynamic fine-grain leakage reduction using leakage-biased bitlines, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Rajendran Panda , David Blaauw, Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.79-90, April 2002
	Amit Agarwal , Hai Li , Kaushik Roy, DRG-cache: a data retention gated-ground cache for low power, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Jingyan Zuo , Abhijit Dharchoudhury , Rajendran Panda , David Blaauw, Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.436-441, June 21-25, 1999, New Orleans, Louisiana, United States
	Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Katsuhiro Seta , Toshiyuki Furusawa, Automated selective multi-threshold design for ultra-low standby applications, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
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	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
	Afshin Abdollahi , Farzan Fallah , Massoud Pedram, Leakage current reduction in CMOS VLSI circuits by input vector control, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.140-154, February 2004
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	Toshinori Sato , Itsujiro Arita, Constructive timing violation for improving energy efficiency, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
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	Vasanth Venkatachalam , Michael Franz, Power reduction techniques for microprocessor systems, ACM Computing Surveys (CSUR), v.37 n.3, p.195-237, September 2005
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