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Approximate reachability with BDDs using overlapping projections
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents
San Francisco, California, United States
Pages: 451 - 456  
Year of Publication: 1998
ISBN:0-89791-964-5
Authors
Shankar G. Govindaraju  Computer Systems Laboratory, Stanford University, Stanford, CA
David L. Dill  Computer Systems Laboratory, Stanford University, Stanford, CA
Alan J. Hu  Department of Computer Science, University of British Columbia, Vancouver, B.C, Canada V6T 1Z4
Mark A. Horowitz  Computer Systems Laboratory, Stanford University, Stanford, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 12,   Downloads (12 Months): 17,   Citation Count: 18
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ABSTRACT

Approximate reachability tec hniques trade off accuracy with the capacity to deal with bigger designs. Cho et al [3] proposed approximate FSM traversal algorithms over a partition of the set of state bits. In this paper w egeneralize it by allowing projectionson to a collection of nondisjoint subsets of the state variables. We establish the adv an tageof ha ving overlapping projections and present a new multiple constr ainfunction for BDDs, to compute efficiently the approximate image during symbolic forward propagation using overlapping projections. We demonstrate the effectiveness of this new algorithm by applying it to several control modules from the I/O unit in the Stanford FLASH Multiprocessor. We also present our results on the larger ISCAS 89 benchmarks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Butch, J. R., Clarke, E. M., McMillan, K. L., Dill, D, L, and Hwang, L. J., "Symbolic Model Checking: 1020 States and Beyond ~' Proceedings of the Conference in Logic in Computer Science, pp. 428-439, 1990.
 
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Cho, H., Hachtel, G., Macii, E., Pleisser, B., and Somenzi, F., "Algorithms for Approximate FSM Traversal Based on State Space Decomposition," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 12, pp. 1465-1478, December 1996.
 
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Cho, H., Hachtel, G., Macii, E., Poncino, M., and Somenzi, F., "Automatic State Space Decomposition for Approximate FSM Traversal Based on Circuit Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 12, pp. 1451-1464, December 1996.
 
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Coudert, O., and Madre, J. C., "A Unified Framework for the Formal Verification of Sequential Circuits," IEEE International Conference on Computer-Aided Design, pp. 126- 129, 1990.
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Touati, H. J., Savoj, H., Lin, B., Bra~on, R. K., and Sangiovanni-Vincentelli, A., "Implicit State Enumeration of Finite State Machines using BDDs,' IEEE International Conference on Computer-Aided Design, pp. 130-133, 1990.

CITED BY  18

Collaborative Colleagues:
Shankar G. Govindaraju: colleagues
David L. Dill: colleagues
Alan J. Hu: colleagues
Mark A. Horowitz: colleagues