A statistical performance simulation methodology for VLSI circuits

ABSTRACT

A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology is accurate because no statistical information about the device parameter variation is lost. It achieves efficiency by analyzing the smaller circuit blocks and generating the performance distribution for the entire circuit. Circuit evaluation at any specified performance level is possible.

REFERENCES

• 1: Reuven Y. Rubinstein, Simulation and the Monte Carlo Method, John Wiley & Sons, Inc., New York, NY, 1981
• 2: J. Power, B. Donnellan, A. Mathewson, W. Lane, "Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst Case Design", IEEE Trans. Semicon. Manuf., August 1994, pp. 306-318.
• 3: Eric Felt , Stefano Zanella , Carlo Guardiani , Alberto Sangiovanni-Vincentelli, Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.374-380, November 10-14, 1996, San Jose, California, United States
• 4: A.N. Lokanathan, J, B, Brockman, "Efficient Worst Case Analysis of Integrated Circuits," 1995 Proc. of CZCC, pp. 237- 240.
• 5: J. Chen, M, Orshansky, C. Hu, C.-P. Wan, "Statistical Circuit Characterization for Deep-Submicron CMOS Designs", 1998 Proc. ZSSCC, pp.90-9 1.
• 6: J. Chen, C. Hu, C.-P. Wan, P. Bendix, A. Kapoor, "E-T Based Statistical Modeling and Compact Statistical Circuit Simulation Methodologies," 1996 Proc. of I~DM, pp. 635-638.
• 7: Jiérâi Vlach , Kishore Singhal, Computer Methods for Circuit Analysis and Design, John Wiley & Sons, Inc., New York, NY, 1993
• 8: J. Chen, C. Hu, Z. Liu, P. Ko, "Realistic Worst-Case SPICE File Extraction Using BSIM3," 1995 Proc. of ~ICC, pp. 375-378.
• 9: $. R. Nassif, "Statistical Worst-Case Analysis for Integrated Circuits", StatisticalApproachto VLSI, pp. 233-253, 1994.
• 10: G.E.P. Box, W. G. Hunter, J. S. Hunter, Statisticsfor Experimenters: An Introduction to Design, Data Analysis, and Model Building, John Wiley & Sons, 1978.
• 11: S.M. Kang, Y. Leblebici, CMOS Digital IntegratedCircuits: AnalysisandDesign, The McGraw-Hill Companies, Inc., 1996.
• 12: M. Hiraki, H. Kojima, H. Misawa, T. Akazawa, Y. Hatano, "Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power 1.3I's", IEEE Journal of Solid-State Circuits, Vol. 30, No.4, April 1995.
• 13: Meta-Software, HSPICE User's Manual, 1996.
• 14: MathSoft Inc, S-Plus, 1994.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  C. Computer Systems Organization

  J. Computer Applications

General Terms:
Design, Measurement, Performance, Theory

Keywords:
custom sizing, migration, timing optimazation