Buffer insertion for noise and delay optimization

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Buffer insertion for noise and delay optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents

San Francisco, California, United States

Pages: 362 - 367

Year of Publication: 1998

ISBN:0-89791-964-5

Authors

Charles J. Alpert	IBM Austin Research Laboratory, Austin, TX
Anirudh Devgan	IBM Austin Research Laboratory, Austin, TX
Stephen T. Quay	IBM Microelectronics Division, Austin, TX

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 42

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ABSTRACT

Buffer insertion has successfully been applied to reduce delay in global interconnect paths; however, existing techniques only optimize delay and timing slack. With the increasing ratio of coupling to total capacitance and the use of aggressive dynamic logic circuit families, noise is becoming a major design bottleneck. We present comprehensive buffer insertion techniques for noise and delay optimization. Our experiments on a microprocessor design show that our approach fixes all noise violations that were identified by a detailed, simulation-based noise analysis tool. Further, we show that the performance penalty induced by optimizing both delay and noise as opposed to only delay is 2%.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Jun Kikuchi , Tetsuo Sasaki , Tohru Hashimoto , Kazuhisa Miyamoto, Delay-optimal wiring plan for the microprocessor of high performance computing machines, Proceedings of the 2000 conference on Asia South Pacific design automation, p.265-270, January 2000, Yokohama, Japan
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