Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis

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Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents

San Francisco, California, United States

Pages: 303 - 308

Year of Publication: 1998

ISBN:0-89791-964-5

Authors

Byron Krauter	IBM Corporation, Austin, TX
Sharad Mehrotra	IBM Corporation, Austin, TX

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 52, Citation Count: 21

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ABSTRACT

It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines [7]. Furthermore, it is also understood that these circuits can be synthesized knowing only the high and the low frequency resistances and inductances [4]. Existing VLSI extraction tools however, are not efficient enough to solve for the frequency dependent resistances and inductances on large VLSI layouts, nor do they synthesize circuits suitable for timing analysis. We propose a rules-based method that efficiently and accurately captures the high and low frequency characteristics directly from layout shapes, and subsequently synthesizes a simple frequency independent ladder circuit suitable for timing analysis. We compare our results to other simulation results.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A.Deutsch,G.V.Kopesay P.Restle et al, "When are Transmission-Line Effects Important for On-Chip Interconnections?" IEEE Transactions on Micmwave Theory and Techniques, No. 10 Oct.1997.
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	4	D.P.Neikirk, Private communication.
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CITED BY 21

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	Yukiko Kubo , Yasuhiro Takashima , Shigetoshi Nakatake , Yoji Kajitani, Self-reforming routing for stochastic search in VLSI interconnection layout, Proceedings of the 2000 conference on Asia South Pacific design automation, p.87-92, January 2000, Yokohama, Japan
	Yehea I. Ismail , Eby G. Friedman , Jose L. Neves, Exploiting the on-chip inductance in high-speed clock distribution networks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.963-973, 12/1/2001
	Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Brian Young , Junfeng Wang , David Blaauw, On-chip inductance modeling and analysis, Proceedings of the 37th conference on Design automation, p.63-68, June 05-09, 2000, Los Angeles, California, United States
	Kaustav Banerjee , Amit Mehrotra, Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects, Proceedings of the 38th conference on Design automation, p.798-803, June 2001, Las Vegas, Nevada, United States
	David Blaauw , Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Junfeng Wang, On-chip inductance modeling, Proceedings of the 10th Great Lakes symposium on VLSI, p.75-80, March 02-04, 2000, Chicago, Illinois, United States
	Guoan Zhong , Cheng Kok Koh , Kaushik Roy, A twisted-bundle layout structure for minimizing inductive coupling noise, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Andrea Pacelli, A local circuit topology for inductive parasitics, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.208-214, November 10-14, 2002, San Jose, California
	Rafael Escovar , Salvador Ortiz , Roberto Suaya, Mutual inductance extraction and the dipole approximation, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao, Inductance 101: analysis and design issues, Proceedings of the 38th conference on Design automation, p.329-334, June 2001, Las Vegas, Nevada, United States
	Shizhong Mei , Yehea I. Ismail, Modeling skin and proximity effects with reduced realizable RL circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.437-447, April 2004
	Hemant Mahawar , Vivek Sarin , Weiping Shi, A solenoidal basis method for efficient inductance extraction, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Akira Tsuchiya , Masanori Hashimoto , Hidetoshi Onodera, Representative frequency for interconnect R(f)L(f)C extraction, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.691-696, January 27-30, 2004, Yokohama, Japan
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	Yu Cao , Xuejue Huang , Dennis Sylvester , Tsu-Jae King , Chenming Hu, Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.1, p.158-162, January 2005
	Akira Tsuchiya , Masanori Hashimoto , Hidetoshi Onodera, Interconnect RL extraction at a single representative frequency, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Ahmed Shebaita , Dusan Petranovic , Yehea Ismail, Importance of volume discretization of single and coupled interconnects, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	M. Mondal , Y. Massoud, Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.691-696, November 06-10, 2005, San Jose, CA
	Laureline David , Stephane Martin , Corinne Cregut , Eric Balossier , Frederic Nyer , Fabrice Huret, Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation, Proceedings of the 7th International Symposium on Quality Electronic Design, p.703-708, March 27-29, 2006
	Chirayu S. Amin , Florentin Dartu , Yehea I. Ismail, Weibull Based Analytical Waveform Model, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.161, November 09-13, 2003
	Mosin Mondal , Yehia Massoud, Accurate loop self inductance bound for efficient inductance screening, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.12, p.1393-1397, December 2006