A mixed nodal-mesh formulation for efficient extraction and passive reduced-order modeling of 3D interconnects

ABSTRACT

As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate three-dimensional interconnect models. In this paper, we describe an integral equation aproach to modeling the impedance of inter-connect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior: Our formulation, based on a combination of nodal and mesh analysis, has the required properties to be combined with Model Order Reduction techniques to generate accurate and guaranteed passive low order Interconnect models for efficient inclusion in standard circuit simulators. Furthermore, the formulation is shown to be more flexible and efficient than previously reported methods.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
  B.8 Performance and Reliability

General Terms:
Design, Measurement, Performance, Reliability, Theory

Keywords:
congestion, global routing, quadratic placement, relaxed pins, routing models, supply-demand