Multi-pad power/ground network design for uniform distribution of ground bounce

ABSTRACT

This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the ground bounce, but to distribute it more evenly among the pads while the routing area is kept to a minimum. We first show that proper p/g terminal to pad assignment is necessary to reduce the maximum ground bounce and then present a heuristic for performing simultaneous assignment and p/g net routing. Experimental results demonstrate the effectiveness of our method.

REFERENCES

• 1: Karl-Heinz Erhard , Frank M. Johannes, Power/ground networks in VLSI: are general graphs better than trees?, Integration, the VLSI Journal, v.14 n.1, p.91-109, Nov. 1992 [doi>10.1016/0167-9260(92)90012-N]
• 2: K.-H. Erhard, F.M. Johannes and R. Dachauer, "Topology Optimization Techniques for Power/Ground Networks in VLSI," Proc. European Design Automation Conference,pp. 362-367, 1992.
• 3: Zahir A. Syed and Abbas E1 Gamal, "Single Layer Routing of Power and Ground Networks in Integrated Circuits," Journal of Digital Systems, vol. 6, no. 1, 1982.
• 4: H. Cai, Multi-pads, single layer power net routing in VLSI circuits, Proceedings of the 25th ACM/IEEE conference on Design automation, p.183-188, June 12-15, 1988, Atlantic City, New Jersey, United States
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• 6: R. Dutta , M. Marek-Sadowska, Automatic sizing of power/ground (P/G) networks in VLSI, Proceedings of the 26th ACM/IEEE conference on Design automation, p.783-786, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74529]
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• 8: Y. Yang, J.R. Brews, "Design Trade-Offs for the Last Stage of an Unregulated, Long-Channel CMOS Off-chip Driver with Simultaneous Switching Noise and Switching Time Consideration," IEEE Trans. on Components, Packaging and Manufacturing Technology- Part B, vol. 19, no. 3, pp. 481- 486, Aug. 1996.
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• 12: See our web site athttp://atrak.usc.edu/~joh

INDEX TERMS

Primary Classification:
  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Routing and layout

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies
  B.8 Performance and Reliability

  C. Computer Systems Organization

  G. Mathematics of Computing
  G.4 MATHEMATICAL SOFTWARE
      Subjects: Algorithm design and analysis

  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
      I.2.8 Problem Solving, Control Methods, and Search
          Subjects: Heuristic methods

  K. Computing Milieux
  K.6 MANAGEMENT OF COMPUTING AND INFORMATION SYSTEMS
      K.6.2 Installation Management
          Subjects: Benchmarks

General Terms:
Algorithms, Design, Experimentation, Measurement, Performance, Standardization, Theory

Keywords:
congestion, global routing, quadratic placement, relaxed pins, routing models, supply-demand