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Potential-NRG: placement with incomplete data
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents
San Francisco, California, United States
Pages: 279 - 282  
Year of Publication: 1998
ISBN:0-89791-964-5
Authors
Maogang Wang  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Prithviraj Banerjee  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Majid Sarrafzadeh  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 4,   Citation Count: 2
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ABSTRACT

T raditional placement problems are studied under a fully specified cell library and a complete netlist. Ho w ev er, in the first, e.g., 2 years of a 2-3 year microprocessor design cycle, the detailed netlist is una vailable. F or area and performance estimation, layout must nev ertheless be done with incomplete information. Another source of incompleteness comes from reuse of instances from earlier design generations; these instances and their parameters will c hange as the project evolves. The problem of placement with incomplete data (PID) can be abstracted as ha ving to place a circuit when pn% of the nets are missing. The key challenge in PID is how to add missing cells and nets. In this paper, tw o “patc hing-methods” for adding missing nets and cells are proposed. The methods are called abstraction and fusion. Experimental results are v ery in teresting and illurstrative. First, they sho w that PID is a difficult problem and an arbitrary (and perhaps intuitiv ely sound) method may not produce high-quality results. Experiments verify that the abstraction method is a very good predictor and that fusion is not because circuits produced by abstraction attain much of the properties of the original circuits. Summary Table 3 in Section 4 shows that when a circuit has 10% incompleteness, abstraction can predict the final total wirelength with an error of 5.8%, while fusion has a 67.8% error in predicting the wirelength in the same circuit.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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M. A. Breuer. "Min-cut Placement". d Design Automation amrl Fault-Tolerant Computing, 1(4):343- 382, 1977.
 
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C.K. Cheng and E. S. Kuh. "Module Placement Based on Resistive Network Optimization". IEEE Transactions on Computer Aided Design, 3(3):218 225, 1984.
 
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3,. E. Dunlop and B. W. KerniOan. "A Procedure for Placement of Standard Cell VLSI Circuits". IEEE Transactions on Computer Aided Design, 4( 1):92-98, January 1985.
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C. Sechen. VLSI Placement and Global Routing Using Simulated Annealing. Kluwer, B. V., Deveuter, 'lhe Netherlands, 1988.
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Collaborative Colleagues:
Maogang Wang: colleagues
Prithviraj Banerjee: colleagues
Majid Sarrafzadeh: colleagues