ACM Home Page
Please provide us with feedback. Feedback
Congestion driven quadratic placement
Full text PdfPdf (216 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents
San Francisco, California, United States
Pages: 275 - 278  
Year of Publication: 1998
ISBN:0-89791-964-5
Authors
Phiroze N. Parakh  University Of Michigan, 1301 Beal Ave, EECS - ACAL, Ann Arbor, MI
Richard B. Brown  University Of Michigan, 1301 Beal Ave, EECS - ACAL, Ann Arbor, MI
Karem A. Sakallah  University Of Michigan, 1301 Beal Ave, EECS - ACAL, Ann Arbor, MI
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 16,   Citation Count: 36
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/277044.277121
What is a DOI?

ABSTRACT

This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring congestion. The algorithm uses an A* router and line-probe heuristics on region-based routing graphs to compute routing cost. The interplay between routing analysis and quadratic placement using a growth matrix permits global treatment of congestion. Further reduction in congestion is obtained by the relaxation of pin constraints. Experiments show improvements in wireability.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
2
3
 
4
E.S. David et. al, "Meshach: Matrix Computations in C". Proceedings of the Center forMathematics and its Applications. Australian National University, vol. 32, 1994.
 
5
G.H. Golub et. al, "Matrix computations", The Johns Hopkins University Press, 2nd ed.
6
 
7
J.M. Kleinhans et. al, "GORDIAN: VLSI placement by quadratic programming and slicing optimization". 1991 IEEE TCADICS, vol. 10, no.3, pp. 356-5.
 
8
P.R. Suaris et. al, "A quadrisection-based combined place and route scheme for standard cells".1989 IEEETCADICS, vol.8, no.3, pp. 234-244.
 
9
 
10
S.-Mayrhofer et. al,"Congestlon-driven placement using a new multi-partitioning heuristic".IEEE ICCAD 90, pp. -332-5.
 
11
S. Prasitjutrakul et. al,"A timinlg-driven global router for custom chip design". 19901EEEICCAD, pp. 48-51.
 
12
S. Yousef, "Iterative methods for sparse linear systems". PWS Publishing Company.
 
13
W. Dongsheng et. al, "Performance-driven interconnect global routing .Proc. 6th GreatLakesSymp'~nVLSl' pp. 132-6.
 
14
Y. Saab, "A fast clustering-based min-cut placement algorithm with simulated-annealing performance". 199~LSI Design, vol.5, no.l, pp. 37-48.

CITED BY  36

Collaborative Colleagues:
Phiroze N. Parakh: colleagues
Richard B. Brown: colleagues
Karem A. Sakallah: colleagues