Hierarchical algorithms for assessing probabilistic constraints on system performance

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Hierarchical algorithms for assessing probabilistic constraints on system performance

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents

San Francisco, California, United States

Pages: 251 - 256

Year of Publication: 1998

ISBN:0-89791-964-5

Authors

G. de Veciana	Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas
M. Jacome	Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas
J.-H. Guo	Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 5, Citation Count: 4

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ABSTRACT

We propose an algorithm for assessing probabilistic performance constraints for systems including components with uncertain delays. We make a case for designing systems based on a probabilistic relaxation of performance constraints, as this has the potential for resulting in lower silicon area and/or power consumption. We consider a concrete example, an MPEG decoder, for which we discuss modeling and assessment of probabilistic throughput constraints.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	In G. De Micheli and M. Sami, editors, Hardware/Software Codesign. Kluwer Academic, 1996.
	2	G. de Veciana, M. Jacome, and J.-H. Guo. Hierarchical algorithms for assessing probabilistic constraints on system performance. Tech. Rep., Dec. 1997.
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CITED BY 4

	Yi-Min Jiang , Kwang-Ting Cheng, Analysis of performance impact caused by power supply noise in deep submicron devices, Proceedings of the 36th ACM/IEEE conference on Design automation, p.760-765, June 21-25, 1999, New Orleans, Louisiana, United States
	Siddharth Garg , Diana Marculescu, System-level throughput analysis for process variation aware multiple voltage-frequency island designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-25, September 2008
	Feng Wang , C. Nicopoulos , Xiaoxia Wu , Yuan Xie , N. Vijaykrishnan, Variation-aware task allocation and scheduling for MPSoC, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	HaNeul Chon , Taewhan Kim, Timing variation-aware task scheduling and binding for MPSoC, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan