Design methodology of a 200MHz superscalar microprocessor: SH-4

ABSTRACT

A new design methodology focusing on high speed operation and short design time is described for the SH-4 200MHz superscalar microprocessor. Random test generation, logic emulation, and formal verification are applied to logic verification for shortening design time. Delay budgeting, forward/back annotation, and clock design are key features for timing driven design.

REFERENCES

• 1: Arakawa, F., eta!., "SH4 RISC Microprocessor far Multimedia," Hot CHIPS IX, Aug., 1997.
• 2: Ishibashi, K., et al., "The Design of 3OOMIPS Microprocessor with a Full Associative TLB far Handheld PC OS," Symp. VLSI Circ. Digest of Technical Papers, pp. 9-10, June, 1997.
• 3: Nishii, 0. et al., "A 200MHz 1.2W 1.4GFLOPS Microprocessor with Graphic Operation Unit, "Int. Solid-State Circ. Conf., Feb., 1998
• 4: Osada, K., et al., "A 2ns Access, 285MHz, Two-Port Cache Macro using Double Global Bit-Line Pairs," ISSCC Digest of Technical Papers, pp. 402-403, 494, Feb., 1997.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Microprocessor/microcomputer applications

Additional Classification:
  C. Computer Systems Organization

General Terms:
Design, Measurement, Performance, Theory, Verification

Keywords:
design methodology, microprocessor, timing, verification