| Boundary element method macromodels for 2-D hierachical capacitance extraction |
| Full text |
Pdf
(289 KB)
|
| Source
|
Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 35th annual Design Automation Conference
table of contents
San Francisco, California, United States
Pages: 218 - 223
Year of Publication: 1998
ISBN:0-89791-964-5
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 4, Downloads (12 Months): 15, Citation Count: 3
|
|
|
ABSTRACT
We presen t a new algorithm for computing the capacitance of three-dimensional perfect electrical conductors of complex structures. The new algorithm is significantly faster and uses muc h less memory than previous best algorithms, and is kernel independent.
The new algorithm is based on a hierarchical algorithm for the n-body problem, and is an acceleration of the boundary-element method for solving the integral equation associated with the capacitance extraction problem. The algorithm first adaptively subdivides the conductor surfaces into panels according to an estimation of the potential coefficients and a user-supplied error band. The algorithm stores the poten tial coefficient matrix in a hierarchical data structure of size O(n), although the matrix is size n2 if expanded explicitly, wheren is the n umber of panels. The hierarchical data structure allows us to multiply the coefficient matrix with an y vector in O(n) time. Finally, w e use a generalized minimal residual algorithm to solve m linear systems each of size n × n in O(mn) time, where m is the n umber of conductors.
The new algorithm is implemented and the performance is compared with previous best algorithms. F or the k × k bus example, our algorithm is 100 to 40 times faster than F astCap, and uses 1/100 to 1/60 of the memory used by F astCap. The results computed by the new algorithm are within 2.7% from that computed by FastCap.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Anand, M.B. et aI. "Fully Integrated Back End of the Line Interconnect Process;' 1994VLSIMultilevellnterconnect Conference, June 7-8, 1994, IEEE 1994 pp. 15-21
|
| |
2
|
Brebbia, C.A; Telles, J.C.F; Wrobel, L.C. Boundury Element Techniques, Springer-Verlag, Berlin, Heidelberg, 1984
|
| |
3
|
Dengi, E.A.; "A Parasitic Capacitance Extraction Method for VLSI Interconnect Modeling", PhD Thesis, Carnegie Mellon University, March 1997
|
 |
4
|
|
| |
5
|
Fukuda, S; Shigyo, N; Kato, K; Nakamura, S. "A ULSI 2-D Capacitance Simulator for Complex Structures Based on Actual Processes," IEEE Trans. Computer-Aided Design, TCAD-9 no. 1, pp.39-47, Jan. 1990
|
| |
6
|
|
| |
7
|
|
| |
8
|
Patterson, C; Sheikh, M.A. "Interelement continuity in the boundary element method," in Topics in Boundury Element Research, Vol. I, C.A. Brebbia (ed.), Springer-Verlag, Berlin, 1984
|
| |
9
|
Ruehli, A.E; Brennan, PA. "Efficient Capacitance Calculations for Three Dimensional Multiconductor Systems,'}rEEE Trans. MicrowaveTheoryTech. MTr-21, pp. 76-82, 1973
|
| |
10
|
|
| |
11
|
~an, G; Lin, F. "Treatment of corner node problems and its singularity," Engineering Analysis with Boundary Elements Vol.13, pp.75-81,1994
|
CITED BY 3
|
|
Eileen You , Lakshminarasimh Varadadesikan , John MacDonald , Wieze Xie, A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits, Proceedings of the 37th conference on Design automation, p.69-74, June 05-09, 2000, Los Angeles, California, United States
|
|
|
|
|
|
|
|