| Boolean matching for large libraries |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 35th annual Design Automation Conference
table of contents
San Francisco, California, United States
Pages: 206 - 211
Year of Publication: 1998
ISBN:0-89791-964-5
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Authors
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Uwe Hinsberger
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HighTec EDV-Systeme GmbH, Feldmannstr. 98, 66119 Saarbrücken, Germany
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Reiner Kolla
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Lehrstuhl für Informatik V Universität Würzburg, Zwinger 34 97070 Würzburg, Germany
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Downloads (6 Weeks): 5, Downloads (12 Months): 14, Citation Count: 9
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ABSTRACT
Boolean matching tackles the problem whether a subcircuit of a boolean network can be substituted by a cell from a cell library. In previous approaches [7, 10, 8] each pair of a subcircuit and a cell is tested for NPN equivalence. This becomes very expensive if the cell library is large. In our approach the time complexity for matching a subcircuit against a library L is almost independent of the size of L. CPU time also remains small for matching a subcircuit against the huge set of functions obtained by bridging and fixing cell inputs; but the use of these functions in technology mapping is very profitable. Our method is based on a canonical representative for each NPN equivalence class. We show how this representative can be computed efficiently and how it can be used for matching a boolcan function against a set of library functions.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang. MIS: A Multiple-Level Logic Optimization System. IEEE Transactions on Computer- Aided Design, CAD-6(6):1062-1081, November 1987.
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E. Detjens, G. Ganot, A. Sangiovanni-Vincentelli, and A. Wang. Technology mapping in MIS. In Proceedings of the International Conference of Computer Aided Design, pages 116-119, 1987.
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U. Hinsberger and R. Kolla. Matching a Boolean Function against a Set of Functions. Technical Report No. 185, Preprint-Reihe, Institut fiir Informatik, Universit,it W/irzburg, 1997.
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U. Hinsberger and R. Kolla. TEMPLATE: a generic TEchnology Mapping PLATform. Technical Report No. 186, Preprint-Reihe, Institut ffir Informatik, Universit/it Wfirzburg, 1997.
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J. Mohnke and S. Malik. Permutation and Phase Independent Boolean Comparison. In Proceedings of the European Design Automation Conference (EDAC93), pages 86-92, 1993.
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Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123421]
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Hamid Savoj , Mário J. Silva , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Boolean matching in logic synthesis, Proceedings of the conference on European design automation, p.168-174, November 1992, Congress Centrum Hamburg, Hamburg, Germany
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S. Yang. Logic Synthesis and Optimization Benchmarks User Guide (Version 3.0). Technical report, Microelectronics Center of North Carolina, P.O. Box 12889, Research Triangle Park, NC 27709, January 1991.
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CITED BY 9
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S. Chatterjee , A. Mishchenko , R. Brayton , X. Wang , T. Kam, Reducing structural bias in technology mapping, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.519-526, November 06-10, 2005, San Jose, CA
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