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Boolean matching for large libraries
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 35th annual Design Automation Conference table of contents
San Francisco, California, United States
Pages: 206 - 211  
Year of Publication: 1998
ISBN:0-89791-964-5
Authors
Uwe Hinsberger  HighTec EDV-Systeme GmbH, Feldmannstr. 98, 66119 Saarbrücken, Germany
Reiner Kolla  Lehrstuhl für Informatik V Universität Würzburg, Zwinger 34 97070 Würzburg, Germany
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 14,   Citation Count: 9
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ABSTRACT

Boolean matching tackles the problem whether a subcircuit of a boolean network can be substituted by a cell from a cell library. In previous approaches [7, 10, 8] each pair of a subcircuit and a cell is tested for NPN equivalence. This becomes very expensive if the cell library is large. In our approach the time complexity for matching a subcircuit against a library L is almost independent of the size of L. CPU time also remains small for matching a subcircuit against the huge set of functions obtained by bridging and fixing cell inputs; but the use of these functions in technology mapping is very profitable. Our method is based on a canonical representative for each NPN equivalence class. We show how this representative can be computed efficiently and how it can be used for matching a boolcan function against a set of library functions.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang. MIS: A Multiple-Level Logic Optimization System. IEEE Transactions on Computer- Aided Design, CAD-6(6):1062-1081, November 1987.
 
2
E. Detjens, G. Ganot, A. Sangiovanni-Vincentelli, and A. Wang. Technology mapping in MIS. In Proceedings of the International Conference of Computer Aided Design, pages 116-119, 1987.
 
3
U. Hinsberger and R. Kolla. Matching a Boolean Function against a Set of Functions. Technical Report No. 185, Preprint-Reihe, Institut fiir Informatik, Universit,it W/irzburg, 1997.
 
4
U. Hinsberger and R. Kolla. TEMPLATE: a generic TEchnology Mapping PLATform. Technical Report No. 186, Preprint-Reihe, Institut ffir Informatik, Universit/it Wfirzburg, 1997.
 
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J. Mohnke and S. Malik. Permutation and Phase Independent Boolean Comparison. In Proceedings of the European Design Automation Conference (EDAC93), pages 86-92, 1993.
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S. Yang. Logic Synthesis and Optimization Benchmarks User Guide (Version 3.0). Technical report, Microelectronics Center of North Carolina, P.O. Box 12889, Research Triangle Park, NC 27709, January 1991.

CITED BY  9

Collaborative Colleagues:
Uwe Hinsberger: colleagues
Reiner Kolla: colleagues