Planning for performance

ABSTRACT

A shift is proposed in the design of VLSI circuits. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing analysis is built into a feedback loop to detect timing violations which are then used to update specifications to synthesis. Such iteration is undesirable, and for very high performance designs, infeasible. The problem is likely to become much worse with future generations of technology. To achieve a non-iterative design flow, we propose that early synthesis stages should use “wireplanning” to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays. In this paper we attempt to quantify this problem for future technologies and propose some solutions for a “constant delay” methodology.

REFERENCES

• 1: H.B. Bakoglu, Circuits, interconnections, and~ackaging for vlsi, Addison-Wesley Pub Co, 1990
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• 3: R.K. Brayton, C.-L. Chen, J.A.G. Jess, R.H.J.M. Otten, L.P.P.P. van Ginneken, Wire planning for stackable designs, Proceedings 1987 International Symposium on VLSl Technology, Systems and Applications, Taipeh, Taiwan, pp 269-273, May 1987
• 4: P.D. Fisher, Clock cycle estimation for future microprocessor generations, 1998
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout
  B.8 Performance and Reliability

  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
      I.2.8 Problem Solving, Control Methods, and Search
          Subjects: Plan execution, formation, and generation

General Terms:
Design, Measurement, Performance, Theory

Keywords:
high-level synthesis, telecommunication