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REMARC (abstract): reconfigurable multimedia array coprocessor
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays table of contents
Monterey, California, United States
Page: 261  
Year of Publication: 1998
ISBN:0-89791-978-5
Authors
Takashi Miyamori
Kunle Olukotun
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): n/a,   Downloads (12 Months): n/a,   Citation Count: 13
Additional Information:

cited by   index terms   collaborative colleagues  

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DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/275107.275164
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CITED BY  13
Reiner Hartenstein, Coarse grain reconfigurable architecture (embedded tutorial), Proceedings of the 2001 conference on Asia South Pacific design automation, p.564-570, January 2001, Yokohama, Japan
R. Hartenstein, A decade of reconfigurable computing: a visionary retrospective, Proceedings of the conference on Design, automation and test in Europe, p.642-649, March 2001, Munich, Germany
Ranga Vemuri , Sriram Govindarajan , Iyad Ouaiss , Meenakshi Kaul , Vinoo Srinivasan , Shankar Radhakrishnan , Sujatha Sundaraman , Satish Ganesan , Awartika Pandey , Preetham Lakshmikanthan, Automated design synthesis and partitioning for adaptive reconfigurable hardware, Hardware implementation of intelligent systems, Physica-Verlag GmbH, Heidelberg, Germany, 2001
Francisco Barat , Rudy Lauwereins , Geert Deconinck, Reconfigurable Instruction Set Processors from a Hardware/Software Perspective, IEEE Transactions on Software Engineering, v.28 n.9, p.847-862, September 2002
Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt, An algorithm for mapping loops onto coarse-grained reconfigurable architectures, ACM SIGPLAN Notices, v.38 n.7, July 2003
Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt, Compilation Approach for Coarse-Grained Reconfigurable Architectures, IEEE Design & Test, v.20 n.1, p.26-33, January 2003
F. Rivera , M. Sanchez-Elez , M. Fernandez , R. Hermida , N. Bagherzadeh, Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
Javier Davila , Alfonso de Torres , Jose Manuel Sanchez , Marcos Sanchez-Elez , Nader Bagherzadeh , F. Rivera, Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys), Proceedings of the conference on Design, automation and test in Europe: Designers' forum, March 06-10, 2006, Munich, Germany
K. Tatas , G. Koutroumpezis , D. Soudris , A. Thanailakis, Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications, Integration, the VLSI Journal, v.40 n.2, p.74-93, February, 2007
Chul Kim , Alex Rassau , Stefan Lachowicz , Mike Myung-Ok Lee , Kamran Eshraghian, 3D-softchip: a novel architecture for next-generation adaptive computing systems, EURASIP Journal on Applied Signal Processing, v.2006 n.1, p.72-72, 01 January
Nikhil Bansal , Sumit Gupta , Nikil Dutt , Alex Nicolau , Rajesh Gupta, Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures, Proceedings of the conference on Design, automation and test in Europe, p.10474, February 16-20, 2004
Bingfeng Mei , Serge Vernalde , Diederik Verkest , Rudy Lauwereins, Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study, Proceedings of the conference on Design, automation and test in Europe, p.21224, February 16-20, 2004
M. Sanchez-Elez , N. Bagherzadeh , R. Hermida, A framework for low energy data management in reconfigurable multi-context architectures, Journal of Systems Architecture: the EUROMICRO Journal, v.55 n.2, p.127-139, February, 2009

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Array and vector processors

  E. Data
  E.3 DATA ENCRYPTION


General Terms:
Design

Collaborative Colleagues:
Takashi Miyamori: colleagues
Kunle Olukotun: colleagues

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