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A 100 MHz PLL implemented on a 100K gate programmable logic device (abstract)
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays table of contents
Monterey, California, United States
Page: 256  
Year of Publication: 1998
ISBN:0-89791-978-5
Authors
David Jefferson
Srinivas Reddy
Christopher Lane
Ninh Ngo
Wanli Chang
Manuel Mijia
Ketan Zaveri
Cameron McClintock
Richard Cliff
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability


General Terms:
Algorithms, Design, Performance

Collaborative Colleagues:
David Jefferson: colleagues
Srinivas Reddy: colleagues
Christopher Lane: colleagues
Ninh Ngo: colleagues
Wanli Chang: colleagues
Manuel Mijia: colleagues
Ketan Zaveri: colleagues
Cameron McClintock: colleagues
Richard Cliff: colleagues

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