A coarse-grained FPGA architecture for high-performance FIR filtering

ABSTRACT

This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.

REFERENCES

• 1: Abnous, A. and Rabaey, J. Ultra-low-power domainspecific multimedia processors, in VLSI Signal Processing IX, IEEE Press, November 1996, 459-468.
• 2: Jeffrey M. Arnold , Duncan A. Buell , Elaine G. Davis, Splash 2, Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures, p.316-322, June 29-July 01, 1992, San Diego, California, United States [doi>10.1145/140901.141896]
• 3: Bergmann, N. W. and Mudge, J. C. Comparing the performance of FPGA-based custom computers with general-purpose computers for DSP applications, in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, April 1994, 164-17 I.
• 4: Patrice Bertin , Didier Roncin , Jean Vuillemin, Programmable active memories: a performance assessment, Proceeding of the 1993 symposium on Research on integrated systems, p.88-102, February 1993, Seattle, Washington, United States
• 5: Oppenheim, A. V. and Schafer, tL W. Digital signal processing. Prentice-Hall, Englewood Cliffs, N.J., 1975.
• 6: Russell J. Petersen , Brad Hutchings, An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing, Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, p.293-302, September 01, 1995
• 7: J. Rabaey, Reconfigurable Processing: The Solution to Low-Power Programmable DSP, Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1, p.275, April 21-24, 1997
• 8: Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing; Layout

  I. Computing Methodologies
  I.5 PATTERN RECOGNITION
      I.5.4 Applications
          Subjects: Signal processing

General Terms:
Algorithms, Design, Experimentation, Performance

Keywords:
architecture, digital signal processing, field programmable gate array, finite impluse response filtering