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 ABSTRACT
Modern field programmable gate arrays (FPGAs) provide embedded memory blocks (EMBs) to be used as on-chip memories. In this paper, we explore the possibility of using EMBs to implement logic functions when they are not used as on-chip memory. We propose a general technology mapping problem for FPGAs with EMBs for area and delay minimization and develop an efficient algorithm based on the concepts of Maximum Fanout Free Cone (MFFC) [3] and Maximum Fanout Free Subgraph (MFFS) [7], named EMB_Pack, which minimizes the area after or before technology mapping by using EMBs while maintaining the circuit delay. We have tested EMB_Pack on MCNC benchmarks on Altera's FLEX10K device family [1]. The experimental results show that compared with the original mapped circuits generated from CutMap [5] without using EMBs, EMB_Pack as postprocessing can further reduce up to 10% of the area on the mapped circuits while maintaining the layout delay by making efficient use of available EMB resources. Compared with CutMap-e without using EMBs, EMB_Pack as pre-mapping processing followed by CutMap-e can reduce 6% of the area while maintaining the circuit optimal delay.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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Altera, 'tProgrammable Logic Devices Data Book", Altera Corp., San Jose, CA, 1996.
|
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2
|
N. Bhat, D. Hill, 'tRoutable Technology Mapping for FP- GAs", First International ACM/SIGDA Workshop on Field Programmable Gate Arrays, Feb. 1992, pp. 143-148.
|
 |
3
|
|
| |
4
|
J. Cong, Y. Ding, UFlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Transactions on Computer- Aided Design, Feb. 1994, Vol. 13, No. 1, pp. 1-12.
|
| |
5
|
J. Cong, Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping", UCLA Computer Science Dept. Tech. Report CSD-950001, January 1995.
|
| |
6
|
|
| |
7
|
Jason Cong , Honching Peter Li , Sung Kyu Lim , Toshiyuki Shibuya , Dongmin Xu, Large scale circuit partitioning with loose/stable net removal and signal flow based clustering, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.441-446, November 09-13, 1997, San Jose, California, United States
|
| |
8
|
Jason Cong , John Peck , Yuzheng Ding, RASP: a general logic synthesis system for SRAM-based FPGAs, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.137-143, February 11-13, 1996, Monterey, California, United States
[doi> 10.1145/228370.228390]
|
| |
9
|
Robert J. Francis , Jonathan Rose , Kevin Chung, Chortle: a technology mapping program for lookup table-based field programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.613-619, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123418]
|
| |
10
|
Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127670]
|
| |
11
|
R. J. Francis, J. Rose, Z. Vranesic, "Technology Mapping for Delay Optimization of Lookup Table-Based FPGAs', MCNC Logic Synthesis Workshop, 1991.
|
| |
12
|
J. He, J. Rose, "Technology Mapping for Heterogeneous FPGAs', Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb. 1994.
|
| |
13
|
Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123421]
|
| |
14
|
R. Murgai, N. Shenoy, R. K. Brayton, A. Sangiovanni- Vincentelli, 'tPerformance Directed Synthesis for Table Look Up Programmable Gate Arrays", Proc. IEEE international Conference on Computer-Aided Design, Nov. 1991, pp. 572- 575.
|
| |
15
|
R. Murgai, N. Shenoy, R. K. Brayton, A. Sangiovanni- VincenteIIi, "Improved Logic Synthesis Algorithms for Table Look Up Architectures", Proc. IEEE International Conference on Computer-Aided Design, Nov. 1991, pp. 564-567.
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16
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CITED BY 19
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Andy Yan , Rebecca Cheng , Steven J. E. Wilton, On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
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Karlheinz Weiß , Thorsten Steckstor , Gernot Koch , Wolfgang Rosenstiel, Exploiting FPGA-features during the emulation of a fast reactive embedded system, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.235-242, February 21-23, 1999, Monterey, California, United States
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Peter Suaris , Lungtien Liu , Yuzheng Ding , Nanchi Chou, Incremental physical resynthesis for timing optimization, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
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