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Sequence-pair based placement method for hard/soft/pre-placed modules
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Source International Symposium on Physical Design archive
Proceedings of the 1998 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 167 - 172  
Year of Publication: 1998
ISBN:1-58113-021-X
Authors
Hiroshi Murata  Department of Electrical Engineering and Computer Science, University of California, Berkeley
Ernest S. Kuh  Department of Electrical Engineering and Computer Science, University of California, Berkeley
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 14,   Downloads (12 Months): 54,   Citation Count: 19
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ABSTRACT

This paper proposes a placement method for a mixed set of hard, soft, and pre-placed modules, based on a placement topology representation called sequence-pair. Under one sequence-pair, a convex optimization problem is efficiently formulated and solved to optimize the aspect ratios of the soft modules. The method is used in two ways: i) directly applied in simulated annealing to present the most exact placement method, ii) applied as a post process in an approximate placement method for faster computation. The performance of these two methods are reported using MCNC benchmark examples.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 15(12):1518- 1524, Dec 1996.
 
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H. Marata, K. Fujiyoshi, T. Watanabe, and Y. Kajitani. A mapping from sequence-pair to rectangular dissection, in Proc. Asia and South Pacific Design Automation Conf. 1997, pages 625-633, 1997.
 
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S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang. An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 12(11):1621-1634, Nov 1993.

CITED BY  19

Collaborative Colleagues:
Hiroshi Murata: colleagues
Ernest S. Kuh: colleagues