LIBRA—a library-independent framework for post-layout performance optimization

ABSTRACT

In this paper we present a post-layout timing optimization framework which (1) is library-independent such that it can take the logic-optimized Verilog file as its input netlist, (2) provides a prototype interface which can communicate with any vendor's physical design tools to obtain the accurate timing, topological and physical information, and perform ECO placement and routing, and (3) has fast and powerful rewiring routines that offer an extra solution space beyond the existing physical-level optimization methodologies. We conduct the post-layout performance optimization experiments on some benchmark circuits which are originally optimized by Synopsys's Design Compiler, (with high timing effort), followed by Avant!'s timing-driven place-and-route tool, Apollo. The optimization strategies we used include rewiring, buffer insertion, and cell sizing. To study the trade-offs between these transformations and the benefits of mixing them together, they are applied both separately and closely integrated by some heuristic cost functions. The result shows that by using all these strategies, post-layout timing optimization can further achieve up to 23.9% of improvement after global routing. We also discuss the pros and cons for our proposed procedures applied after global routing versus after detail routing. Some factors that can affect the quality of rewiring such as level of recursive learning and type of rewiring will also be addressed.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Algorithms, Design, Experimentation, Performance