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Partitioning using second-order information and stochastic-gain functions
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Source International Symposium on Physical Design archive
Proceedings of the 1998 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 112 - 117  
Year of Publication: 1998
ISBN:1-58113-021-X
Authors
Shantanu Dutt  EECS Dept., Univ. of Illinois at Chicago
Halim Theny  Intel Corp., Folsom, CA
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 6,   Citation Count: 4
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ABSTRACT

A probability-based partitioning algorithm, PROP, was introduced in [5] that achieved large improvements over traditional “deterministic” iterative-improvement techniques like FM [7] and LA [10]. While PROP's gain function has a greater futuristic component than FM or LA, it incorporates spatially local information—only information on the removal probabilities of adjacent nets of a cell is used in its gain computation. This prevents a higher-level view of non-local structures. Also, giving uniform weights to all nets, results in an inability to differentiate between the futuristic benefit of removing one net from another. In this paper, we present a more sophisticated partitioner DEEP-PROP that incorporates more non-local (second-order) structural information than PROP. The second-order information is incorporated into cell gains as well as variable net weights—the latter helps to focus future cell moves in a cluster around the currently moved cell and thus better utilizes the information that led to its selection. A lower-complexity version, VAR-PROP, that also uses dynamically assigned variable net weights, but based on first-order information, has also been developed. Both versions yield significant improvements over PROP on the ACM/SIGDA benchmark suite. DEEP-PROP yields mincut improvements of as much as 39% for large circuits and an average improvement of 20% over all circuits; it is about 3.8 times slower than PROP, which is very fast. VAR-PROP, which has a much lower computational complexity than DEEP-PROP, yields maximum and average mincut improvements over PROP of 27% and 12%, respectively, while being only about 1.14 times slower.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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(22. Alp~ and A.B. Kahn~ "A hybrid rnullileveFge~efic approach for circuit partitioning" PID'sical Design gbrkshop, 1995, pp. 100- 105.
 
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S. Hauck and G. Bordello, "An Evaluation of Bipartitioning Techniques", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 8, pp. 849-866, August 1997.
 
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B.W. Kemighan and S. Lin, "An efficient heuristic procedure for partitioning graphs", BellSystem Tech. Journal, vol. 49, February 1970, pp. 291-307.
 
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B. Kfishnamurthy, "An improved mineut algorithm for partitioning VLSI networks", IEEE Trans. on Computers, vol. C-33, no. 5, May 1984, pp. 438-446.
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Collaborative Colleagues:
Shantanu Dutt: colleagues
Halim Theny: colleagues