Global wires: harmful?

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Global wires: harmful?

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International Symposium on Physical Design archive
Proceedings of the 1998 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 104 - 109

Year of Publication: 1998

ISBN:1-58113-021-X

Author

Ralph H. J. M. Otten

Delft University of Technology, The Netherlands, University of California at Berkeley, California and Synopsys Inc., Mountain View, California

Sponsors

IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 26, Citation Count: 23

Additional Information:

abstract references cited by index terms collaborative colleagues

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ABSTRACT

In this paper a shift is proposed in the design of vlsi circuits. In conventional design higher levels of synthesis have to deliver a gate and net list, from which layout synthesis has to built a mask specification for manufacturing. Analysis, mainly timing analysis, is built in a feedback loop to catch violations of timing requirements before sign-off. These violations are used to hand an updated specification to synthesis. Such iteration is not desirable, and for really high performance not feasible. To come to a design flow, higher level synthesis should distribute delay over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	A. E. Caldwell , A. B. Kahng , I. L. Markov, Optimal partitioners and end-case placers for standard-cell layout, Proceedings of the 1999 international symposium on Physical design, p.90-96, April 12-14, 1999, Monterey, California, United States
	Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron II: a global wiring paradigm, Proceedings of the 1999 international symposium on Physical design, p.193-200, April 12-14, 1999, Monterey, California, United States
	Probir Sarkar , Vivek Sundararaman , Cheng-Kok Koh, Routability-driven repeater block planning for interconnect-centric floorplanning, Proceedings of the 2000 international symposium on Physical design, p.186-191, May 2000, San Diego, California, United States
	Jason Cong , Tianming Kong , David Zhigang Pan, Buffer block planning for interconnect-driven floorplanning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.358-363, November 07-11, 1999, San Jose, California, United States
	Ralph H. J. M. Otten , Giuseppe S. Garcea, Are wires plannable?, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.59-66, March 31-April 01, 2001, Sonoma, California, United States
	Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.203-211, November 08-12, 1998, San Jose, California, United States
	Hung-Ming Chen , D. F. Wong , Wai-Kei Mak , Hannah H. Yang, Faster and more accurate wiring evaluation in interconnect-centric floorplanning, Proceedings of the 11th Great Lakes symposium on VLSI, p.62-67, March 2001, West Lafayette, Indiana, United States
	Ralph H. J. M. Otten , Paul Stravers, Challenges in physical chip design, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Jason Cong , Majid Sarrafzadeh, Incremental physical design, Proceedings of the 2000 international symposium on Physical design, p.84-92, May 2000, San Diego, California, United States
	Yuantao Peng , Xun Liu, Power macromodeling of global interconnects considering practical repeater insertion, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Xun Liu , Yuantao Peng , Marios C. Papaefthymiou, Practical repeater insertion for low power: what repeater library do we need?, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Hua Xiang , D. F. Wong , Xiaoping Tang, An algorithm for integrated pin assignment and buffer planning, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Jason Cong , Tianming Kong , Zhigang (David) Pan, Buffer block planning for interconnect planning and prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.929-937, 12/1/2001
	Andrew B. Kahng , Stefanus Mantik, On mismatches between incremental optimizers and instance perturbations in physical design tools, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Hua Xiang , Xiaoping Tang , Martin D. F. Wong, An algorithm for integrated pin assignment and buffer planning, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.3, p.561-572, July 2005
	Yuantao Peng , Xun Liu, Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Yuantao Peng , Xun Liu, A sensitivity analysis of low-power repeater insertion, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Edmund Lee , Guy Lemieux , Shahriar Mirabbasi, Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays, Journal of Signal Processing Systems, v.51 n.1, p.57-76, April 2008
	Yuantao Peng , Xun Liu, Low-power repeater insertion with both delay and slew rate constraints, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	C. J. Alpert , Jiang Hu , S. S. Sapatnekar , C. N. Sze, Accurate estimation of global buffer delay within a floorplan, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.706-711, November 07-11, 2004
	Xun Liu , Yuantao Peng , Marios C. Papaefthymiou, RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power, Proceedings of the conference on Design, Automation and Test in Europe, p.1330-1335, March 07-11, 2005
	David A. Papa , Tao Luo , Michael D. Moffitt , C. N. Sze , Zhuo Li , Gi-Joon Nam , Charles J. Alpert , Igor L. Markov, RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Tao Luo , David A. Papa , Zhuo Li , C. N. Sze , Charles J. Alpert , David Z. Pan, Pyramids: an efficient computational geometry-based approach for timing-driven placement, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California