Filling and slotting: analysis and algorithms

ABSTRACT

In very deep-submicron VLSI, certain manufacturing steps &mdash notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)&mdash have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future place-and-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.

REFERENCES

• 1: tLBek, C. C.I~andJ.tLIJu, personal commmdcation" December 1997.
• 2: Cadence Design Systems, Inc. Dracula Starutalone Verification Reference, November 1997.
• 3: L. E.. Camilletti, "Implementation of CMP-based Design Rules and Patterning Practices", 1995 1EEElSEMI Advanced Semiconductor Manufacturing Conference, pp. 2-4.
• 4: W. B. Glendinning and J. N. Helbert, Handbook of VLSI Microlithography: Principles, Technology, and Applications, Noyes Publications, 1991.
• 5: S.W. Golomb. Polyomfnoes. Scn'bner, New Yofl~, 1965.
• 6: M. Hanzn, "On Steiner's Problem with Rectilinear Distance", SIAMJ. Applied Math. 14 (196ff), pp. 255-265.
• 7: A. Kahng , G. Robins , C. Singh , A. Wang , A. Zelikovsky, Filling and Scotting: Analysis and Algorithms, University of Virginia, Charlottesville, VA, 1997
• 8: H. Landis, P. Burke, W. Cote, W. ~IL C. Hoffman, C. Kaantn, C. Koburger, W. Lauge, M. Leach and S. Luce, "Integration of Chemical-Mechanical Polishing into CMOS Integrated Circuit Manufacturing; Thin Solid H/ms, 220(1992), pp. 1-7.
• 9: Franco P. Preparata , Michael I. Shamos, Computational geometry: an introduction, Springer-Verlag New York, Inc., New York, NY, 1985
• 10: 1L Radojcie, personal communfcaaon, March 1996.
• 11: P. Rai-Choudhury, cal., Handbook ofMicrolithography, Micromachining, and Microfabrica~n, voL 1: Microlithography, Bellingham, SPIE OptiealEngineering Press, 1997.
• 12: "SEMATECH Demonstrates New Insulator For Faster Chips", Business W/re, Nov. 11, 1997.
• 13: Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, December 1997.
• 14: K. Wampler and T. Laidig, personal communication, Sept. 1997.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing; Layout

General Terms:
Algorithms, Design, Performance, Theory, Verification