CHDStd—application support for reusable hierarchical interconnect timing views

ABSTRACT

This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first review EDA requirements for CHDStd hierarchy for large complex leading edge chips and current EDA problems in accurately and efficiently handling complex interconnect. We then describe our approach for fully-reusable hierarchical interconnect timing views in support of timing driven design for 0.25µ technologies and below. The result is a method which builds on SEMATECH's new controlled error parasitic timing calculation capability for deep submicron, providing means for compactly storing and reusing accurate hierarchical timing views for 28M to 100M transistor chip designs.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout; Placement and routing

General Terms:
Design, Performance, Standardization