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Timing metrics for physical design of deep submicron technologies
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Source International Symposium on Physical Design archive
Proceedings of the 1998 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 28 - 33  
Year of Publication: 1998
ISBN:1-58113-021-X
Author
Lawrence Pileggi  Department of Electrical and Computer Engineering, Carnegie Mellon University
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 6,   Downloads (12 Months): 53,   Citation Count: 7
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ABSTRACT

Performance-driven physical design is becoming more important as advances in IC technologies enable gigahertz operating frequencies. These same IC technologies, however, exhibit dominant interconnect resistance, non-negligible coupling capacitance, and even the potential for inductance effects, which makes the performance modeling and prediction more difficult. In this tutorial paper we will overview some of the existing timing metrics that are suitable for use during physical design, and introduce new metrics and directions for future work.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
H.B. Bakoglu, Circuits, Intercormections, and Packaging for V/~I, Addison-Wesley Publishing Company, 1990.
 
2
C. Chu and M. Homwitz, Charge-Sharing Models for Switch-Level Simulation. IEEE Trans. on Computer-Aided Design, 6(6):1053-1060, 1987.
3
4
 
5
W.C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, J. AppL Phys.,19(1):55-63, 1948.
 
6
P. Feldmann and ILW. Freund, Efficient Linear Circuit Analysis by Pad6 Approximation via the Lanczos Process, IEEE Trans. on CAD, vol. 14, no. 5, May 1995.
7
 
8
M.A. Horowitz, Timing Models for MOS Circuits, Ph.D. thesis, Stanford University, January 1984.
 
9
10
 
11
12
 
13
 
14
S.P. McCormick, Modeling and Simulation of VLSI Interconnections with Moments, Ph.D. Thesis, MIT, Jun. 1989.
 
15
P.R. O'Brien and T.L. Savadno, Modeling the driving-point characteristic of resistive interconnect for accurate delay estimarion, Proc. IEEE Intl. Conf. Computer-Aided Design, November, 1989.
 
16
A. Odabasioglu, E. Acar, L.T. Pileggi, S2P: Stable Two Pole Model, CMU Technical Report, January, 1998.
 
17
 
18
 
19
L.T. Pillage and R.A. Rohrer, Asymptotic waveform evaluation for timing analysis, IEEE Trans. Computer-Aided Design, vol. 9, no. 4, pp. 352-366, April 1990.
 
20
D.A. Priore, Inductance on Silicon for Sub-Micron CMOS VLSI," IEEE Symposium on VLSI Circuits, 1993.
21
 
22
J. Rubenstein, P. Penfield, Jr., and M. A. Horowitz, Signal delay in RC tree networks, IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983.
 
23
24
25
 
26
G.Yee, R. Chandra, V.Ganesan, C. Sechen, Wier Delay in the Presence of Crosstalk, In Proceedings of the TAU Workshop on Timing in Digital Systems, December, 1997.

CITED BY  7