Silicon trends and limits for advanced microprocessors

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Silicon trends and limits for advanced microprocessors

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Communications of the ACM archive
Volume 41 , Issue 3 (March 1998) table of contents

Pages: 80 - 87

Year of Publication: 1998

ISSN:0001-0782

Author

Mark Bohr

Intel Corp's Portland Technology

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 9, Downloads (12 Months): 60, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Agnello, P., Newman, T., Crabbe, E., Subbanna, S., Ganin, E., Liebmann, L., Comfort, J., and Sunderland, D. Phase edge lithography for sub-0.1 btm electrical channel length in a 200mm full CMOS process. In Tech. Dig. of the Symposium on VLSI Technology (Kyoto, June 6-8, 1995), IEEE Press, Piscataway, N.J., pp. 79-80.
	2	Asai, S., and Wada, Y. Technology challenges for integration near and below 0.1btm. Proc. IEEE 85, 4 (April 1997), 505-520.
	3	Bohr, M. Interconnect scaling--The real limiter to high-performance ULSI. In Tech. Dig. of the International Electron Devices Meeting (Washington, D.C., Dec. 10-13, 1995), IEEE Press, Piscataway, N.J., pp. 241-244.
	4	Bohr, M., Ahmed, S., Brigham, L., Chau, R., Gasser, R., Green, R., Hargrove, W., Lee, E., Natter, R., Thompson, S., Weldon, K., and Yang, S. A high-performance 0.35btm logic technology for 3.3V and 2.5V operation. In Tech. Dig. of the International Electron Devices Meeting (San Francisco, Dec. 11-14, 1994), IEEE Press, Piscataway, N.J., pp. 273-276.
	5	Bohr, M., Ahmed, S., Ahmed, S., Bost, M., Ghani, T., Greason, J., Hainsey, R., Jan, C., Packan, P., Sivakumar, S., Thompson, S., Tsai, J., and Yang, S. A high-performance 0.25 btm logic technology optimized for 1.8V operation. In Tech. Dig. of the International Electron Devices Meeting (San Francisco, Dec. 8-11, 1996), IEEE Press, Piscataway, N.J., pp. 847-850.
	6	Dennard, R., Gaensslen, F., Yu, H., Rideout, V., Bassous, E., and LeBlanc, A. Design of ion-implanted MOSFETs with very small physical dimensions. IEEE ft. Solid State Circuits SC-9, 5 (Oct. 1974), 256-268.
	7	Taur, Y., Buchanan, D., Chen, W., Frank, D., Ismail, K., Lo, S., Sai- Halasz, G., Viswanathan, R., Wann, H., Wind, S., and Wong, H,. CMOS scaling into the nanometer range. Proc. IEEE 85, 4 (April 1997), 486-504.

CITED BY 3

	Glenn Reinman , Todd Austin , Brad Calder, A scalable front-end architecture for fast instruction delivery, ACM SIGARCH Computer Architecture News, v.27 n.2, p.234-245, May 1999
	Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli, Performance analysis and optimization of latency insensitive systems, Proceedings of the 37th conference on Design automation, p.361-367, June 05-09, 2000, Los Angeles, California, United States
	V. Chandra , H. Schmit , A. Xu , L. Pileggi, A power aware system level interconnect design methodology for latency-insensitive systems, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.275-282, November 07-11, 2004