The SimpleScalar tool set, version 2.0

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The SimpleScalar tool set, version 2.0

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ACM SIGARCH Computer Architecture News archive
Volume 25 , Issue 3 (June 1997) table of contents

Pages: 13 - 25

Year of Publication: 1997

ISSN:0163-5964

Authors

Doug Burger	Computer Sciences Department, University of Wisconsin-Madison, 1210 West Dayton Street, Madison, Wisconsin
Todd M. Austin	Computer Sciences Department, University of Wisconsin-Madison, 1210 West Dayton Street, Madison, Wisconsin

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ACM New York, NY, USA

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Downloads (6 Weeks): 38, Downloads (12 Months): 199, Citation Count: 146

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ABSTRACT

This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern microprocessors. The new release offers more tools and capabilities, precompiled binaries, cleaner interfaces, better documentation, easier installation, improved portability, and higher performance. This paper contains a complete description of the tool set, including retrieval and installation instructions, a description of how to use the tools, a description of the target SimpleScalar architecture, and many details about the internals of the tools and how to customize them. With this guide, the tool set can be brought up and generating results in under an hour (on supported platforms).

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	Konrad Malkowski , Padma Raghavan , Mahmut Kandemir , Mary Jane Irwin, Phase-aware adaptive hardware selection for power-efficient scientific computations, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Greg Stitt , Frank Vahid, Thread warping: a framework for dynamic synthesis of thread accelerators, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
	Krishnan Sundaresan , Nihar R. Mahapatra, An analysis of timing violations due to spatially distributed thermal effects in global wires, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Amit Golander , Shlomo Weiss, Hiding the misprediction penalty of a resource-efficient high-performance processor, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.4, p.1-32, January 2008
	Kaveh Jokar Deris , Amirali Baniasadi, Investigating cache energy and latency break-even points in high performance processors, ACM SIGARCH Computer Architecture News, v.35 n.4, September 2007
	Kyoungwoo Lee , Aviral Shrivastava , Minyoung Kim , Nikil Dutt , Nalini Venkatasubramanian, Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach, Proceeding of the 16th ACM international conference on Multimedia, October 26-31, 2008, Vancouver, British Columbia, Canada
	Roger Kahn , Shlomo Weiss, Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers, Microprocessors & Microsystems, v.32 n.8, p.425-436, November, 2008
	David Bermingham , Liu Zhen , Xiaojun Wang, SimNP: a flexible platform for the simulation of a network processing system, Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, November 06-07, 2008, San Jose, California
	Roman Lysecky, Scalability and parallel execution of warp processing: dynamic hardware/software partitioning, International Journal of Parallel Programming, v.36 n.5, p.478-492, October 2008
	Prasad A. Kulkarni , David B. Whalley , Gary S. Tyson , Jack W. Davidson, Practical exhaustive optimization phase order exploration and evaluation, ACM Transactions on Architecture and Code Optimization (TACO), v.6 n.1, p.1-36, March 2009
	Yen-Jen Chang , Mao-Feng Lan, Two new techniques integrated for energy-efficient TLB design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.1, p.13-23, January 2007
	Xi E. Chen , Tor M. Aamodt, Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.59-70, November 08-12, 2008
	Roman Lysecky , Frank Vahid, Design and implementation of a MicroBlaze-based warp processor, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.3, p.1-22, April 2009
	Jun Yao , Shinobu Miwa , Hajime Shimada , Shinji Tomita, A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases, IEICE - Transactions on Information and Systems, v.E91-D n.4, p.1010-1022, April 2008
	Mikael Collin , Mats Brorsson, Two-Level Dictionary Code Compression: A New Scheme to Improve Instruction Code Density of Embedded Applications, Proceedings of the 2009 International Symposium on Code Generation and Optimization, p.231-242, March 22-25, 2009
	Demid Borodin , B. H. Juurlink , Said Hamdioui , Stamatis Vassiliadis, Instruction-Level Fault Tolerance Configurability, Journal of Signal Processing Systems, v.57 n.1, p.89-105, October 2009
	D. Novo , T. Schuster , B. Bougard , A. Lambrechts , L. Perre , F. Catthoor, Energy-performance Exploration of a CGA-based SDR Processor, Journal of Signal Processing Systems, v.56 n.2-3, p.273-284, September 2009
	Yangchun Luo , Venkatesan Packirisamy , Wei-Chung Hsu , Antonia Zhai , Nikhil Mungre , Ankit Tarkas, Dynamic performance tuning for speculative threads, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009
	Stijn Eyerman , Lieven Eeckhout , Tejas Karkhanis , James E. Smith, A mechanistic performance model for superscalar out-of-order processors, ACM Transactions on Computer Systems (TOCS), v.27 n.2, p.1-37, May 2009