The future of logic synthesis and physical design in deep-submicron process geometries

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The future of logic synthesis and physical design in deep-submicron process geometries

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 218 - 224

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Kurt Keutzer	Synopsys Inc., 700 E. Middlefield Rd., Mountain View CA
A. Richard Newton	University of California, Department of Electrical Engineering and Computer Science, Berkeley CA
Narendra Shenoy	Synopsys Inc., 700 E. Middlefield Rd., Mountain View, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 23, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 7

	Victor N. Kravets , Karem A. Sakallah, M32: a constructive multilevel logic synthesis system, Proceedings of the 35th annual conference on Design automation, p.336-341, June 15-19, 1998, San Francisco, California, United States
	Jason Cong , Majid Sarrafzadeh, Incremental physical design, Proceedings of the 2000 international symposium on Physical design, p.84-92, May 2000, San Diego, California, United States
	Hema Kapadia , Mark Horowitz, Using partitioning to help convergence in the standard-cell design automation methodology, Proceedings of the 36th ACM/IEEE conference on Design automation, p.592-597, June 21-25, 1999, New Orleans, Louisiana, United States
	Hsiao-Pin Su , Allen C.-H. Wu , Youn-Long Lin, Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy, Proceedings of the 1998 international symposium on Physical design, p.12-17, April 06-08, 1998, Monterey, California, United States
	Wilsin Gosti , Amit Narayan , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Wireplanning in logic synthesis, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.26-33, November 08-12, 1998, San Jose, California, United States
	Chien Chu Kuo , Allen C. H. Wu, Delay budgeting for a timing-closure-driven design method, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	A. I. Erzin , J. D. Cho, Concurrent Placement and Routing in the Design of Integrated Circuits, Automation and Remote Control, v.64 n.12, p.1988-1999, December 2003