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Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century
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Source International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents
Napa Valley, California, United States
Pages: 212 - 217  
Year of Publication: 1997
ISBN:0-89791-927-0
Authors
R. G. Bushroe  SEMATECH, 2706 Montopolis Drive, Austin, Texas
S. DasGupta  IBM Corporation, 11400 Burnett Road, Austin, Texas
A. Dengi  Motorola Inc., 3501 Ed Bluestein Blvd., Austin, Texas
P. Fisher  SEMATECH, 2706 MontopolIs Drive, Austin, Texas
S. Grout  SEMATECH, 2706 MontopolIs Drive, Austin, Texas
G. Ledenbach  SEMATECH, 2706 MontopolIs Drive, Austin, Texas
N. S. Nagaraj  SEMATECH, 2706 MontopolIs Drive, Austin, Texas
R. Steele  SEMATECH, 2706 MontopolIs Drive, Austin, Texas
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 7,   Citation Count: 6
Additional Information:

references   cited by   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
"Design Needs for the 21st Century: White Paper," Semiconductor Research Center (SRC), September, 1994
 
2
The National Technology Roadmap for Semiconductors, pp 5-43. Semiconductor Industry Association (SIA), 1994
 
3
J. Y. Sayah , R. Gupta , D. D. Sherlekar , P. S. Honsinger , J. M. Apte , S. W. Bollinger , H. H. Chen , S. DasGupta , E. P. Hsieh , A. D. Huber , E. J. Hughes , Z. M. Kurzum , V. B. Rao , T. Tabtieng , V. Valijan , D. Y. Yang, Design planning for high-performance ASICs, IBM Journal of Research and Development, v.40 n.4, p.431-452, July 1996
 
4
Standard Delay Calculation Specification, vl.0. Open VERILOG International (OVI) -- Cad Framework Initiative (CF0 Joint Publication, April, 1996
 
5
Requirements Document - SEM TECH ECAD Program CI-IDS Technical Data (CHDStd) - Requirements for a Chip Hierarchical Product Design Specification Needed to Support 0.25-micron Chip Design. SEMATECH, October 6, 1995
 
6
Chip Hierarchical Design System - Integrated I-Iierarehical Forward Tirn~g Driven Electrical and Physical Design Requirements for 0.25-micron Chip Design, Version 1.0. SEMATECH, February 21, 1996
 
7
EDA Industry Standards Roadmap for Design and Test, Version 1.0, published jointly by EDAC, CFI, and SEMATECH, January 15, 1996
 
8
Mark T. Bohr, "Intercennect Sealing - The Real Ltmiter to High Performance UI~I," Proceedings of the IEDM, 1995, pp. 241-244
 
9
An Integrated Data Model for Hierarchical Design Assembly, May 31, 1996, published jointly by IBM and CFI via http://www.efi.org/CHDStd/infomodegidm.infomodel_overview.h tml
 
10
CHDStd Information Model Documentation, January 27, 1996, published by CFI via http://www'efi'~rg/CI'IDStd/ehdsIndex'html
 
11
CHDS Information Exchange Needs, January 28, 1996, published jointly by CFI and SEMATECH via http://www.efi.org/malli~w._paper/idrn refs.html

CITED BY  6
Albert Wang , Earl Killian , Dror Maydan , Chris Rowen, Hardware/software instruction set configurability for system-on-chip processors, Proceedings of the 38th conference on Design automation, p.184-188, June 2001, Las Vegas, Nevada, United States
S. Grout , G. Ledenbach , R. G. Bushroe , P. Fisher , D. Cottrell , D. Mallis , S. DasGupta , J. Morrell , Amrich Chokhavtia, CHDStd—application support for reusable hierarchical interconnect timing views, Proceedings of the 1998 international symposium on Physical design, p.75-79, April 06-08, 1998, Monterey, California, United States
Hsiao-Pin Su , Allen C.-H. Wu , Youn-Long Lin, Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy, Proceedings of the 1998 international symposium on Physical design, p.12-17, April 06-08, 1998, Monterey, California, United States
Jason Cong , Majid Sarrafzadeh, Incremental physical design, Proceedings of the 2000 international symposium on Physical design, p.84-92, May 2000, San Diego, California, United States
Alok Mehrotra , Lukas van Ginneken , Yatin Trivedi, Design flow and methodology for 50M gate ASIC, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
Lun Ye , Foong-Charn Chang , Peter Feldmann , Nagaraj Ns , Rakesh Chadha , Frank Cano, Chip-level verification for parasitic coupling effects in deep-submicron digital designs, Proceedings of the conference on Design, automation and test in Europe, p.128-es, January 1999, Munich, Germany

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  J. Computer Applications

  K. Computing Milieux
  K.1 THE COMPUTER INDUSTRY
      Subjects: Suppliers


General Terms:
Design, Performance, Theory, Verification

Collaborative Colleagues:
R. G. Bushroe: colleagues
S. DasGupta: colleagues
A. Dengi: colleagues
P. Fisher: colleagues
S. Grout: colleagues
G. Ledenbach: colleagues
N. S. Nagaraj: colleagues
R. Steele: colleagues

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