Preserving HDL synthesis hierarchy for cell placement

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Preserving HDL synthesis hierarchy for cell placement

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 169 - 174

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Yu-Wen Tsay	Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China
Wen-Jong Fang	Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China
Allen C.-H. Wu	Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China
Youn-Long Lin	Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan, 300, Republic of China

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 13, Citation Count: 2

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Y. C. Wei and C.K. Cheng, "Ratio cut partitiomng for hierarchical designs," IEEE Trans. on Compter- Aided Design, voI.CAD-10, pp.911-921, July 1991.
	2	Sujit Dey, France Beglez and Gershon Kedem, "Circuit partitioning for logic synthesis," IEEE Journal of Solid-Stage Oireuits, voi.26, pp.350-363, March 1991.
	3	Gotaro Odawara, Takahisa Hiraide and Osamu Nishina, "Partitioning and placemen~ technique for CMOS gate arrays," IBBB Trans. o~ Compter- Aided Design, vol.CAD-6, pp.355-363, May 1987.
	4	Yu-Wen Tsay and Youn-Long Lin, "A Row-Based Cell Placement Method That Utilizes Circuit Structural Properties," IBBB Trans. or~ Compter-Aided Design, vol.14, no. 3, March 1995.
	5	Wen-Jong Fang , Allen C.-H. Wu , Duan-Ping Chen, Module generation of complex macros for logic-emulation applications, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.69-75, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258314]
	6	E. K. Sentovich et al., "SIS: A System for Sequential Circui~ Synthesis," U.O. Berkeley Technical Report UCB/ERL M92/41, May 1992.
	7	Donald M. Schuler , Ernst G. Ulrich, Clustering and linear placement, Proceedings of the 9th workshop on Design automation, p.50-56, June 26-28, 1972 [doi>10.1145/800153.804929]
	8	C. Sechen, "TimberWolf6.0: Mixed macrostandard cell floor planning, placement and routing package," user's manual, Yale University, Sep., 1991.
	9	TSMC450 Library, Taiwan Semeconductor Manufacturing Co. Ltd.
	10	"Cell Ensemble Reference Manual Version 4,3.4", Cadence, 1996.

CITED BY 2

	Andrew B. Kahng, Classical floorplanning harmful?, Proceedings of the 2000 international symposium on Physical design, p.207-213, May 2000, San Diego, California, United States
	Hsiao-Pin Su , Allen C.-H. Wu , Youn-Long Lin, Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy, Proceedings of the 1998 international symposium on Physical design, p.12-17, April 06-08, 1998, Monterey, California, United States