A matrix synthesis approach to thermal placement

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A matrix synthesis approach to thermal placement

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 163 - 168

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Chris C. N. Chu	Department of Computer Sciences, University of Texas at Austin, Austin, TX
D. F. Wong	Department of Computer Sciences, University of Texas at Austin, Austin, TX

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 19, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Kai-Yuan Chao , D. F. Wong, Thermal placement for high-performance multichip modules, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.218-223, October 02-04, 1995
	3	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	4	M. D. Osterman and M. Pecht. Component placement for reliability on conductively cooled printed wiring boards. ASME J. of Packaging, 111(3):149-156, 1989,
	5	M. D. Osterman and M. Pecht. Placement for reliability and routability of convectively coded PWBs, IEEE Transactions on GAD, 9(7):734-744, 1990.
	6	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996 [doi>10.1145/225871.225877]
	7	B. T. Preas and M. J. Lorenzetti. Physical Design A u. tomation of VLSI Systems. Benjamin Cummings, Menlo Park, CA, 1988.
	8	R. E. Simons. Micro electronics cooling and SemiTherm, A look back. in Proceedings of the l Oth Semiconductor Thermal and Temperature Measurement Symposium, pages 1-16, 1994.

CITED BY 13

	Craig Beebe , Jo Dale Carothers , Alfonso Ortega, MCM placement using a realistic thermal model, Proceedings of the 10th Great Lakes symposium on VLSI, p.189-192, March 02-04, 2000, Chicago, Illinois, United States
	Ching-Han Tsai , Sung-Mo (Steve) Kang, Standard cell placement for even on-chip thermal distribution, Proceedings of the 1999 international symposium on Physical design, p.179-184, April 12-14, 1999, Monterey, California, United States
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Temperature-aware resource allocation and binding in high-level synthesis, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Peak temperature control and leakage reduction during binding in high level synthesis, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Brent Goplen , Sachin Sapatnekar, Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.86, November 09-13, 2003
	Yuan Xie , Gabriel H. Loh , Bryan Black , Kerry Bernstein, Design space exploration for 3D architectures, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.2 n.2, p.65-103, April 2006
	Pilok Lim , Taewhan Kim, Thermal-aware high-level synthesis based on network flow method, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Zuoyuan Li , Xianlong Hong , Qiang Zhou , Jinian Bian , Hannah H. Yang , Vijay Pitchumani, Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.325-345, April 2006
	Sheng-Chih Lin , Kaustav Banerjee, An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	J. Cong , Jie Wei , Yan Zhang, A thermal-driven floorplanning algorithm for 3D ICs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.306-313, November 07-11, 2004
	W.-L. Hung , G. M. Link , Yuan Xie , N. Vijaykrishnan , M. J. Irwin, Interconnect and Thermal-aware Floorplanning for 3D Microprocessors, Proceedings of the 7th International Symposium on Quality Electronic Design, p.98-104, March 27-29, 2006
	Brent Goplen , Sachin Spatnekar, Placement of 3D ICs with thermal and interlayer via considerations, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Rajarshi Mukherjee , Seda Ogrenci Memik, An integrated approach to thermal management in high-level synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.11, p.1165-1174, November 2006