Power optimization for FPGA look-up tables

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Power optimization for FPGA look-up tables

Full text

Pdf (855 KB)

Source

International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 156 - 162

Year of Publication: 1997

ISBN:0-89791-927-0

Author

Michael J. Alexander

School of Electrical Engineering and Computer Science, Washington State University

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 29, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/267665.267707 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S.B. AKERS, Binary Decison Diagrams, IEEE Trans. on Computers, C- 27 (1978), pp. 509-516.
	2	M.J. ALEXANDER, Power Optimization for FPGA Look-Up Table#, Tech. Rep. EECS-9?-001, School of Electrical Engineering and Computer Science, Washington State University, January 1997.
	3	Gaetano Borriello , Carl Ebeling , Scott A. Hauck , Steven Burns, The triptych FPGA architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.4, p.491-501, Dec. 1995 [doi>10.1109/92.475968]
	4	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	5	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	6	Bradley S. Carlson , C. Y. Roger Chen, Performance enhancement of CMOS VLSI circuits by transistor reordering, Proceedings of the 30th international conference on Design automation, p.361-366, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164931]
	7	E. CERNY, D. MANGE, AND E. SANCHEZ, Synthesis of Minimal Binary Decision Trees, IEEE Trans. on Computers, C-28 (1979), pp. 472-482.
	8	D.-S. CHEH, S. SARRAFZADEI{, AND G. K. H. YEAP, S~ate Encoding ol Finite State Machines for Low Power Design, in Proc. IEEE Intl. Syrup. Circuits and Systems, 1995, pp. 2309-2312.
	9	S. DEVADAS, K. KEUTZER, AND J. WHITE, Estimation of Poteer Dissipation in CMOS Combinational Circuits, in Custom Integrated Circuits Conf., 1990, pp. 19.7.1-19.7.6.
	10	Amir H. Farrahi , Majid Sarrafzadeh, System partitioning to maximize sleep time, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.452-455, November 05-09, 1995, San Jose, California, United States
	11	Amir H. Farrahi , Gustavo E. Téllez , Majid Sarrafzadeh, Memory segmentation to exploit sleep mode operation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.36-41, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217503]
	12	Amir H. Farrahi , Majid Sarrafzadeh, FPGA Technology Mapping for Power Minimization, Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications, p.66-77, September 07-09, 1994
	13	B. LIN AND H. D~MAN, Low-Power Driven Technology Mapping under Timing Constraints, in Proc. IEEE Intl. Conf. Computer Design, Cambridge, MA, October 1993, pp. 421-427.
	14	M. MAREK-SA~)OWSKA AND 5. P. LIN, Pin A ssign~n.ent j'or Improved Performance in Standard Cell Design, in Proc. IEEE Intl. Conf. Computer Design, October 1990, pp. 339-342.
	15	Bernard M. E. Moret, Decision Trees and Diagrams, ACM Computing Surveys (CSUR), v.14 n.4, p.593-623, Dec. 1982 [doi>10.1145/356893.356898]
	16	R. PANWAR AND D. RENNELS, Input ordering for Low Power in CMOS Logic Gates, Intl. Journal of Electronics, 78 (1995), pp. 925-943.
	17	M. PEDRAM, Power Rstimation and Optimization at the Logic Level, International Journal on High-Speed Electronics and Systems, 5 (1994), pp. 179-202.
	18	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996 [doi>10.1145/225871.225877]
	19	Michel Robert , Lionel Torres , F. Moraes , Daniel Auvergne, Influence of Locig Block Layout Architecture on FPGA Performance, Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications, p.34-44, September 07-09, 1994
	20	Kaushik Roy , Sharat Prasad, SYCLOP: Synthesis of CMOS Logic for Low Power Applications, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.464-467, October 11-14, 1992
	21	D. SINGH, J. M. RABEY, M. PEDRAM, F. CATTHOOR, 5. RAJGOPAL, N. SI~HGAL, AND T. J. MOZDZEN, Power Conscious CAD Tools and Methodologies: A Perspective, Proc. IEEE; 83 (1995), pp. 570-594.
	22	C.H. TAN AND J. ALLEN, Minimization of Power in VLSI Circuits Using Transistor Sizing, Input ordering, and Statistical Power Estimation, in Proc. International Workshop on Low Power Design, 1994, pp. 75-$0.
	23	Gustavo E. Téllez , Amir Farrahi , Majid Sarrafzadeh, Activity-driven clock design for low power circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.62-65, November 05-09, 1995, San Jose, California, United States
	24	Stephen Trimberger, Effects of FPGA architecture on FPGA routing, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.574-578, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217592]
	25	Stephen M. Trimberger, Field-Programmable Gate Array Technology, Kluwer Academic Publishers, Norwell, MA, 1994
	26	Benjamin Tseng , Jonathan Rose , Stephen Dean Brown, Improving FPGA Routing Architectures Using Architecture and CAD Interactions, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.99-104, October 11-14, 1992
	27	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Technology decomposition and mapping targeting low power dissipation, Proceedings of the 30th international conference on Design automation, p.68-73, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164577]
	28	Jean E. Vuillemin , Patrice Bertin , Didier Roncin , Mark Shand , Hervé H. Touati , Philippe Boucard, Programmable active memories: reconfigurable systems come of age, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.1, p.56-69, March 1996 [doi>10.1109/92.486081]
	29	XILINX, The Programmable Gate Array Data Book, Xillnx, Inc., San Jose, California, 1996.

CITED BY 2

	Balakrishna Kumthekar , Luca Benini , Enrico Macii , Fabio Somenzi, In-place power optimization for LUT-based FPGAs, Proceedings of the 35th annual conference on Design automation, p.718-721, June 15-19, 1998, San Francisco, California, United States
	Hyung Gyu Lee , Kyungsoo Lee , Yongseok Choi , Naehyuck Chang, Cycle-Accurate Energy Measurement and Characterization of FPGAs, Analog Integrated Circuits and Signal Processing, v.42 n.3, p.239-251, March 2005