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How good are slicing floorplans?
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Source International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents
Napa Valley, California, United States
Pages: 144 - 149  
Year of Publication: 1997
ISBN:0-89791-927-0
Authors
F. Y. Young  Department of Computer Sciences, The University of Texas at Austin
D. F. Wong  Department of Computer Sciences, The University of Texas at Austin
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 20,   Citation Count: 4
Additional Information:

references   cited by   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Brenda S. Baker, Jr. E.G. Coffman, and Ronald L. Rivest. Orthogonal packings in two dimension. SIAM J. Uomputing~ 9(4):846-855, 1980.
 
2
Jr E.G. Coffman, M.R. Garey, D.S. Johnson, and R.E. Tarja. Performance bounds for level-oriented two-dimensional packing algorithms. SIAM J. Oomputing, 9(4):808--826, 1980.
 
3
D.P. Lapotin and S.W. Director. A new algorithm for floorplan design. Proceedings IEEE International Uonference on Computer-Aided Design~ pages 143-145, 1985.
 
4
Ralph H.J.M. Otten, Automatic floorplan design, Proceedings of the 19th conference on Design automation, p.261-267, January 1982
 
5
Takayuki Yamanouchi , Kazuo Tamakashi , Takashi Kambe, Hybrid floorplanning based on partial clustering and module restructuring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.478-483, November 10-14, 1996, San Jose, California, United States
 
6
D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States

CITED BY  4
F. Y. Young , D. F. Wong, Slicing floorplans with pre-placed modules, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.252-258, November 08-12, 1998, San Jose, California, United States
M. Lai , D. Wong, Slicing tree is a complete floorplan representation, Proceedings of the conference on Design, automation and test in Europe, p.228-232, March 2001, Munich, Germany
Jason Cong , Gabriele Nataneli , Michail Romesis , Joseph R. Shinnerl, An area-optimality study of floorplanning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
Silke Salewski , Erich Barke, An Upper Bound for 3D Slicing Floorplans, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.567, January 07-11, 2002

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Routing and layout


General Terms:
Design, Measurement, Performance, Theory, Verification

Collaborative Colleagues:
F. Y. Young: colleagues
D. F. Wong: colleagues

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