On two-step routing for FPGAS

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On two-step routing for FPGAS

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 60 - 66

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Guy G. F. Lemieux	Department of Electrical and Computer Engineering, University of Toronto, Canada
Stephen D. Brown	Department of Electrical and Computer Engineering, University of Toronto, Canada
Daniel Vranesic	Department of Electrical and Computer Engineering, University of Toronto, Canada

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 16, Citation Count: 18

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 18

	Seokjin Lee , Hua Xiang , D. F. Wong , Richard Y. Sun, Wire type assignment for FPGA routing, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Yao-Wen Chang , Kai Zhu , D. F. Wong, Timing-driven routing for symmetrical array-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.433-450, July 2000
	Gi-Joon Nam , Karem A. Sakallah , Rob A. Rutenbar, Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.167-175, February 21-23, 1999, Monterey, California, United States
	G. Nam , K. Sakallah , R. Rutenbar, A boolean satisfiability-based incremental rerouting approach with application to FPGAs, Proceedings of the conference on Design, automation and test in Europe, p.560-565, March 2001, Munich, Germany
	Yao-Wen Chang , Yu-Tsang Chang, An architecture-driven metric for simultaneous placement and global routing for FPGAs, Proceedings of the 37th conference on Design automation, p.567-572, June 05-09, 2000, Los Angeles, California, United States
	Yao-Wen Chang , Kai Zhu , Guang-Ming Wu , D. F. Wong , C. K. Wong, Analysis of FPGA/FPIC switch modules, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.1, p.11-37, January 2003
	Vaughn Betz , Jonathan Rose, Automatic generation of FPGA routing architectures from high-level descriptions, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.175-184, February 10-11, 2000, Monterey, California, United States
	Herman Schmit , Vikas Chandra, FPGA switch block layout and evaluation, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Nak Woong Eum , Taewhan Kim , Chong Min Kyung, A router for symmetrical FPGAs based on exact routing density evaluation, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	K. K. Lee , Martin D. F. Wong, LRoute: a delay minimal router for hierarchical CPLDs, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.12-20, February 2001, Monterey, California, United States
	Narendra V. Shenoy , Jamil Kawa , Raul Camposano, Design automation for mask programmable fabrics, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation, IEEE Transactions on Computers, v.53 n.7, p.829-842, July 2004
	Herman Schmit , Vikas Chandra, Layout techniques for FPGA switch blocks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.1, p.96-105, January 2005
	Jai-Ming Lin , Song-Ra Pan , Yao-Wen Chang, Graph matching-based algorithms for array-based FPGA segmentation design and routing, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Siva Nageswara Rao Borra , Annamalai Muthukaruppan , S. Suresh , V. Kamakoti, A novel approach to the placement and routing problems for field programmable gate arrays, Applied Soft Computing, v.7 n.1, p.455-470, January, 2007
	Keith So, Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Seokjin Lee , Yongseok Cheon , Martin D. F. Wong, A Min-Cost Flow Based Detailed Router for FPGAs, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.388, November 09-13, 2003
	Aman Gayasen , Vijaykrishnan Narayanan , Mahmut Kandemir , Arifur Rahman, Designing a 3-D FPGA: switch box architecture and thermal issues, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.882-893, July 2008