VLSI/PCB placement with obstacles based on sequence-pair

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VLSI/PCB placement with obstacles based on sequence-pair

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 26 - 31

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

H. Murata	Japan Advanced Institute of Science and Technology, Japan
K. Fujiyoshi	Tokyo University of Agriculture and Technology, Japan
M. Kaneko	Japan Advanced Institute of Science and Technology, Japan

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 28, Citation Count: 15

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
	2	M. C. Chi, An automatic rectilinear partitioning procedure for standard cells, Proceedings of the 24th ACM/IEEE conference on Design automation, p.50-55, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37895]
	3	Lu Sha , Robert W. Dutton, An analytical algorithm for placement of arbitrarily sized rectangular blocks, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.602-608, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317952]
	4	A. Alon and U. Asehex, "Model and Solution Strategy for Placement of Rectangular Blocks in the Euclidean Plane," IEEE Trans. on GAD, vol. 7, no. 3, pp. 378- 386, 1988.
	5	D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States
	6	Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
	7	T. T~ashi, "Aa Algorithm for Finding a Maximum- Weight Decreasing Sequence in a Permutation, Motivated by Rectangle Packing Problem," Technical Report of IEIGE, vol. VLD96, no. 201, pp. 31-35, 1996.

CITED BY 15

	Kunihiro Fujiyoshi , Hiroshi Murata, Arbitrary convex and concave rectilinear block packing using sequence-pair, Proceedings of the 1999 international symposium on Physical design, p.103-110, April 12-14, 1999, Monterey, California, United States
	Xiaoping Tang , Ruiqi Tian , D. F. Wong, Fast evaluation of sequence pair in block placement by longest common subsequence computation, Proceedings of the conference on Design, automation and test in Europe, p.106-111, March 27-30, 2000, Paris, France
	Xiaoping Tang , D. F. Wong, FAST-SP: a fast algorithm for block placement based on sequence pair, Proceedings of the 2001 conference on Asia South Pacific design automation, p.521-526, January 2001, Yokohama, Japan
	F. Y. Young , D. F. Wong, Slicing floorplans with pre-placed modules, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.252-258, November 08-12, 1998, San Jose, California, United States
	M. Lai , D. Wong, Slicing tree is a complete floorplan representation, Proceedings of the conference on Design, automation and test in Europe, p.228-232, March 2001, Munich, Germany
	Hiroshi Murata , Ernest S. Kuh, Sequence-pair based placement method for hard/soft/pre-placed modules, Proceedings of the 1998 international symposium on Physical design, p.167-172, April 06-08, 1998, Monterey, California, United States
	Jianbang Lai , Ming-Shiun Lin , Ting-Chi Wang , Li-C. Wang, Module placement with boundary constraints using the sequence-pair representation, Proceedings of the 2001 conference on Asia South Pacific design automation, p.515-520, January 2001, Yokohama, Japan
	Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
	Guang-Ming Wu , Yun-Chih Chang , Yao-Wen Chang, Rectilinear block placement using B*-trees, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.188-202, April 2003
	Evangeline F. Y. Young , Chris C. N. Chu , M. L. Ho, Placement constraints in floorplan design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.735-745, July 2004
	Jai-Ming Lin , Yao-Wen Chang, TCG-S: orthogonal coupling of P*-admissible representations for general floorplans, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	F. Y. Young , D. F. Wong, Slicing floorplans with range constraint, Proceedings of the 1999 international symposium on Physical design, p.97-102, April 12-14, 1999, Monterey, California, United States
	Evangeline F. Y. Young , M. L. Ho , Chris C. N. Chu, A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.661, January 07-11, 2002
	Sheng-Ta Hsieh , Tsung-Ying Sun , Chan-Cheng Liu , Cheng-Wei Lin, An improved particle swarm optimizer for placement constraints, Journal of Artificial Evolution and Applications, v.8 n.2, p.1-10, January 2008
	Jill H. Y. Law , Evangeline F. Y. Young, Multi-bend bus driven floorplanning, Integration, the VLSI Journal, v.41 n.2, p.306-316, February, 2008