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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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AHK96
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C. J. Alpert, L. W. Hagen, and A. B. Kahng. "A Hybrid Multilevel/Genetic Approach for Circuit Partitioning." In Ptoc. ACM/SIGDA PJ~ydcal Design Workshop, pp. 100-105, 1996.
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Alp96
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BCL87
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Bre76
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M. A. Breuer. ':Min-cut Placement." Design Automation and Fault-Tolerant Computing, I(4):343-362, 1976.
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Bre77
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DD96a
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DD96b
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S. Dutt and W. Deng. "VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques." In Proc, A CM/SIGDA Physical Design Workshop, pp. 92-99, 1996. Also see corresponding Technical Report, Dept. of Electrical Engineering, U. Minnesota.
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DJA94
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K. Doll, F. M. Johannes, and K. J. Antreich. "Iterative Placement Improvement by Network Flow Methods." IEEE Transactions on Computer- Aided Design, 13:1189-1200, 1994.
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DJS94
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K. Doll, F. M. 3ohannes, and G. Sigl. "Iteratire Placement Improvement by Network Flow Methods," IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 13(10):1189-1199, 1994.
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DK85
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A.E. Dunlop and B. W. Kernighan. "A Procedure for Placement of Standard Cell VLSI Circuits." IEEE Transactions on Computer-Aided Design, 4(1):92-98, 1985.
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FM82
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HHK95
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KL70
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B.W. Kernighan and S. Lin. "An Efficient Heuristic Procedure for Partitioning Graphs." Bell Syst, Tech. J., 49(2):291-307, 1970.
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KSJ91
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J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization." IEEE Transactions on Computer-Aided Design, 10(3):356-365, 1991.
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Lau79
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Len90
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RE95
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B.M. Riess and G. G. Ettelt. ``SPEED: Fast and Efficient Timing Driven Placement." In Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 377-380, 1995.
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San89
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San93
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SDJ91
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Georg Sigl , Konrad Doll , Frank M. Johannes, Analytical placement: A linear or a quadratic objective function?, Proceedings of the 28th conference on ACM/IEEE design automation, p.427-432, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127707]
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SK87a
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P.R. Suaris and G. Kedem. "Quadrisection: A New Approach to Standard Cell Layout." in Pracee&'ngs of the IEEE/AUM International Conference on Computer-Aided Design, pp. 474-477, 1987.
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SK87b
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P.R. Suaris and G. Kedem. "Standard Cell Placement by Quadrisection." In Proceedings IEEE Intl. Conf. Computer Design, pp. 612-615, 1987.
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SK88
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P.R. Suaris and G. Kedem. "An Algorithm for Quadrisection and Its Application to Standard Cell Placement." IEEE Transactions on Circuits and Systems, 35(3}:294-303, 1988.
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SK89
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P.R.. Suaris and G. Kedem. "A Quadrisectionbased Combined Place and Route Scheme for Standard Cells." IEEE Transactions on Computer-Aided Design, 8(3):234-244. 1989.
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SM91
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SS93
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SS95
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Ste97
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G. Stenz. 1997. Personal communication.
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Swa96
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W. Swartz, 1996. Personal communication.
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TK91
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R.-S. Tsay and E. S. Kuh. "A Unified Approach to Partitioning and Placement." IEEE Transactions on Circuits and Systems, 38(5):521-533, 1991.
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TKH88
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CITED BY 28
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Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States
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Charles J. Alpert , Jen-Hsin Huang , Andrew B. Kahng, Multilevel circuit partitioning, Proceedings of the 34th annual conference on Design automation, p.530-533, June 09-13, 1997, Anaheim, California, United States
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Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Hypergraph partitioning with fixed vertices, Proceedings of the 36th ACM/IEEE conference on Design automation, p.355-359, June 21-25, 1999, New Orleans, Louisiana, United States
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A. B. Kahng , I. Mandoiu , P. Pevzner , S. Reda , A. Zelikovsky, Engineering a scalable placement heuristic for DNA probe arrays, Proceedings of the seventh annual international conference on Research in computational molecular biology, p.148-156, April 10-14, 2003, Berlin, Germany
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Saurabh N. Adya , Mehmet C. Yildiz , Igor L. Markov , Paul G. Villarrubia , Phiroze N. Parakh , Patrick H. Madden, Benchmarking for large-scale placement and beyond, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
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C. J. Alpert , A. E. Caldwell , A. B. Kahng , I. L. Markov, Partitioning with terminals: a “new” problem and new benchmarks, Proceedings of the 1999 international symposium on Physical design, p.151-157, April 12-14, 1999, Monterey, California, United States
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